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OSVVM Webinar December 15 and Classes

December 13, 2016 in Announcement, Event, OS-VVM in general

Webinar From OSVVM to UCIS Database. Thursday December 15, 2016

When a simulator records functional coverage internally, it gains the ability to correlate the functional coverage with its verification planning tools and share that information with safety critical tools.

The 2016.11 release of Open Source VHDL Verification Methodology (OSVVM) adds an API to record OSVVM Functional Coverage directly into a simulator’s UCIS database.

This task has been on our todo list for quite some time. UCIS is complicated. Fortunately the engineers at Aldec were up to creating an initial implementation. Together we revised it.

Join OSVVM architect and VHDL trainer, Jim Lewis, and Aldec Software Product Manager, Radek Nawrot, for a presentation and demonstration of how to add this capability to your VHDL testbench.

Europe Session 3-4 pm CET 6-7 am PST 9-10 am EST Enroll with Aldec
US Session 11 am -12 noon PST 2-3 pm EST 8-9 pm CET Enroll with Aldec

OSVVM World Tour Training Dates

VHDL Testbenches and Verification – OSVVM+ Boot Camp

Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

January 16-20 and January 30-February 3 Web Class Enroll with SynthWorks
February 20-25 Freiburg, Germany Enroll with PLC2
March 6-10 Nordic Region Enroll with FirstEDA
March 13-17 and March 27-31 Web Class Enroll with SynthWorks
April 17-21 and May 1-5 Web Class Enroll with SynthWorks
May 8-12 Freiburg, Germany Enroll with PLC2
May 22-26 Bracknell, UK Enroll with FirstEDA

OSVVM on GitHub, OSVVM Training in Germany, and other OSVVM Training Datess

February 10, 2016 in Announcement, Event, OS-VVM in general

OSVVM on GitHub
OSVVM is now on GitHub. You can find releases there. I will be putting bug patches there first before formally releasing them on OSVVM.org. Long term I also plan on putting tool specific branches as needed (such as for Cadence).

https://github.com/JimLewis/OSVVM

OSVVM Training in Germany
In conjunction with PLC2, we will be offering OSVVM training in Germany. See the matrix below for the first two dates in Freiburg, Germany.

OSVVM Training Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

February 29 – March 4 Freiburg, Germany Enroll with PLC2
March 28 – April 1 and April 11-15 online class Enroll with SynthWorks
April 25-29 Stockholm, Sweden Enroll with FirstEDA
May 9-13 Freiburg, Germany Enroll with PLC2
May 23-27 and June 13-17 online class Enroll with SynthWorks
July 25-29 and August 8-12 online class Enroll with SynthWorks
September 12-16 Bracknell, UK Enroll with FirstEDA

Upcoming OSVVM Events

October 18, 2015 in Event

OSVVM Presentation in Copenhagen
IDA is hosting an OSVVM presentation on 9 November 2015 from 18:30 til 20:30.  For details see:  http://ida.dk/event/316127

OSVVM and Error Reporting
DVCon Europe in Munich, Germany.  See:  DVCon-Europe Program

OSVVM World Tour Training Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

November 16-20 Copenhagen, Denmark Enroll with FirstEDA
November 30 – December 4 and December 14-18 online class Enroll with SynthWorks
January 11-15 and January 25-29 online class Enroll with SynthWorks
February 1-5 Bracknell, UK Enroll with FirstEDA

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

OSVVM Webinar (June 25th) and Classes

June 22, 2015 in Event, Functional Coverage, OS-VVM in general, Randomization

Webinar OSVVM for VHDL Testbenches. Thursday June 25, 2015
Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology. Like UVM, OSVVM is a library of free, open-source code (packages). OSVVM uses this library to implement functional coverage, constrained random tests, and Intelligent Coverage random tests with a conciseness, simplicity and capability that rivals other verification languages.

In 2015, OSVVM added comprehensive error and message reporting (January, 2015.01) and memory modeling (June, 2015.06). With this expanded capability, this presentation
takes a look at the big picture methodology progressing transactions to randomization to functional coverage to intelligent coverage to alerts (error reporting) and logs (message reporting) to memory modeling.

Worried about keeping up with the latest trends in verification? With Intelligent Coverage, OSVVM has a portable, VHDL-based, intelligent testbench solution built into the library. While Accellera is still working on their Intelligent testbench based portable stimulus solution (in the Portable Stimulus Working Group -PSWG), for OSVVM it is already here. Best of all, OSVVM is free and works in any VHDL simulator that support a minimal amount of VHDL-2008.

Europe Session 3-4 pm CEST 6-7 am PDT 9-10 am EDT Enroll with Aldec
US Session 10-11 am PDT 1-2 pm EDT 7-8 pm CEST Enroll with Aldec

OSVVM World Tour Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

July 20-24 and August 3-7 online class Enroll with SynthWorks
September 14-18 Bracknell, UK Enroll with FirstEDA
September 21-25 and October 5-9 online class Enroll with SynthWorks
October 26-30 Portland, OR (Tigard/Tualatin) Enroll with SynthWorks
November 9-13 Copenhagen, Denmark Enroll with FirstEDA
November 16-20 and November 30 – December 4 online class Enroll with SynthWorks

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

OSVVM™ Webinar and World Tour Dates

June 20, 2014 in Event, Functional Coverage, OS-VVM in general

Webinar Thursday June 26, 2014
OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests. This simplified approach allows you to utilize advanced randomization techniques when you need them and easily mix advanced randomization techniques with directed, algorithmic, and file-based test generation techniques. Best of all, OSVVM is free, works in all of Aldec and some other VHDL simulators.

Europe Session 3-4 pm CEST 6-7 am PDT 9-10 am EDT Enroll with Aldec
US Session 11 am-12 Noon PDT 2-3 pm EDT 8-9 pm CEST Enroll with Aldec

OSVVM World Tour Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

July 14-18 Munich, Germany Enroll with eVision Systems
July 21-25 Bracknell, UK Enroll with FirstEDA
August 18-22 and September 2-5 online class Enroll with SynthWorks
August 25-29 Portland, OR (Tigard/Tualatin) Enroll with SynthWorks
September 15-19 Gothenburg, Sweden Enroll with FirstEDA
October 20-24 Bracknell, UK Enroll with FirstEDA
October 27-31 and November 10-14 online class Enroll with SynthWorks
November 17-21 Baltimore, MD (BWI Area) Enroll with SynthWorks
December 1-5 and December 17-21 online class Enroll with SynthWorks

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

OSVVM World Tour

March 19, 2014 in Event, OS-VVM in general

In conjunction with FirstEDA, I taught the first two European sessions of our OSVVM and Transaction Level Modeling (TLM) focused Advanced VHDL Testbenches and Verification class. We had attendees from many of the major European System Companies who design and verify programmable devices (FPGAs). The skill level of the delegates was impressive and made teaching one of my favorite classes just that much more fun.

Not only is VHDL dominant in Europe, but according to the 2012 Wilson Research Functional Verification Study, VHDL is the dominant FPGA design and verification language worldwide. See figures 3 and 5 of the study.

When combined with Transaction Level Modeling (TLM), OSVVM provides VHDL with an advanced verification methodology that is competitive if not superior to SystemVerilog and UVM. While OSVVM provides advanced features, such as constrained random (good), Intelligent Coverage based randomization (better), and functional coverage (essential for any randomization based methodology), verification is not just about advanced features – it is also about simplicity, readability and familiarity of the approach – not by just verification engineers, but also by RTL engineers.

Take the next step in your VHDL Verification methodology. Join us on the OSVVM world tour of our Advanced VHDL Testbenches and Verification class.

The class next dates are below. More dates will be announced shortly. Enrollment information or links are available at SynthWorks Class Schedule

  • Baltimore, Maryland April 7-11
  • UK April 28-May 2
  • Gothenburg, Sweden May 5-9
  • On-line May 12-16 and May 27-30
  • Munich Germany July 14-18
  • UK July 21-25

Webinar Recording: VHDL Intelligent Coverage using OSVVM

August 1, 2013 in Event, OS-VVM in general

Did you miss the SynthWorks and Aldec webinar on Intelligent Coverage and Open Source VHDL Verification Methodology (OSVVM)?

The slides and recorded webinar (on Aldec’s site) are now available. You may also be interested in reading our OSVVM Blog posts.

Looking to learn more about OSVVM and further advance your VHDL testbench skills, attend SynthWorks’ VHDL Testbenches and Verification class. In this class, we provide a super set of the OSVVM packages that facilitate transaction level modeling (tlm), self-checking, scoreboards, memory modeling, synchronization methods, functional coverage, and randomization. Our modeling approach is accessible by both verification and RTL designers.

We have instructor-led online classes coming up on September 3-6 and September 16-20. We have a public venue class session on August 19-23 in Portland, Oregon.  Class details and enrollment information are here:
http://www.synthworks.com/public_vhdl_courses.htm#VHDL_Test_Bench_Training

Webinar about OS-VVM coming soon. Any questions?

July 12, 2012 in Event, Functional Coverage, OS-VVM in general, Randomization

Hello Fellow OS-VVMers,

A webinar introducing OS-VVM is coming soon. It will be broadcast twice on July 19th, 2012 (Thursday):

If you plan to attend, please register using links above. There will be a chance to ask questions during the webinar, but if you already have questions, please ask them now in the replies (comments) to this post. The most interesting ones will be answered live during the webinar — your name will not be mentioned unless you explicitly give us permission in the reply (something like this: “You can call me John from Chicago while answering my question.”)

Hope to see you during the webinar!

Your Friendly Admin.

Let’s Meet At DAC…

May 16, 2012 in Event, OS-VVM in general, VHDL in general

Semi-formal meeting of OS-VVM fans and VHDL users will be held at the 49th Digital Automation Conference (DAC 2012). The conference is located in San Francisco, California, USA this year. The entry to the exhibit hall at Moscone Center is free on Monday, June 4th – drop in if you happen to be in the area.

We are meeting at the ALDEC booth (#2126) at 2pm. To help us estimate how many visitors can appear, please reply to the forum post or use Contact Us form.

See you in San Francisco!