Reply To: Vivado : Error with AXI Data width

Hi Jim,
I updated the AXI FULL OSVVM testbench available here.

architecture TestHarness of TbAxi4 is
  constant AXI_ADDR_WIDTH : integer := 16 ;
  constant AXI_DATA_WIDTH : integer := 256 ;
  constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ;

I modified the width of AXI DATA and AXI ADDR, and adapted the test cases to include the new data and address sizes.

  ManagerProc : process
    variable send_Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ;
    variable send_Addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0) ;
    variable y : integer;

  begin
    wait until nReset = '1' ;  
    WaitForClock(ManagerRec, 2) ; 
    for y in 0 to 10 loop
     send_Addr := ( '1', others => '0') ;
     send_Data := ( '0', '1' ,others => '0');
     Write(ManagerRec, send_Addr, send_Data) ;
     WaitForClock(ManagerRec, 10) ; 

    end loop;

    WaitForClock(ManagerRec, 2) ;
    WaitForBarrier(TestDone) ;
    wait ;
  end process ManagerProc ;

Regards,
Remy