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Jim Lewis replied to the topic Compiling UART testbench.pro in Questa in the forum OSVVM 4 years, 1 month ago
Hi Graeme,
You need to dobuild ../UART/testbench/testbench.proIn OSVVM,
buildandincludeuse a path reference relative to the script they are running.
Hence, in testbench.pro, it just saysanalyze TestCtrl_e.vhd. The path to testbench.pro gets
automatically prepended onto the file name. Hence, when writing scripts we only need to know
the…[Read more] -
Graeme started the topic Compiling UART testbench.pro in Questa in the forum OSVVM 4 years, 1 month ago
Have created a sim_dir under OsvvmLibraries_2021_09
Have compiled the osvvv, Common + UART libraries by calling the relevant .pro files
e.g.
build ../UART/UART.proNo probs so far
When I try to execute
build ../UART/testbench/testbench.pro I get this error
####################
####################
do ../UART/testbench/testbench.pro
# vmap…[Read more] -
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Jim Lewis wrote a new post 4 years, 1 month ago
As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM.
At this […]
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Jim Lewis wrote a new post 4 years, 1 month ago
In reply to a LinkedIn post that regurgitated the old statement that VHDL is verbose, I replied, “With the VHDL-2008 update, Verilog is more verbose than VHDL.”
This led my old friend Cliff Cummings and I to […]
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Musab Ahmet became a registered member 4 years, 1 month ago
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