Open Source VHDL Verification Methodology | Ashok | Activity https://osvvm.org/members/ashokmehta72/activity Activity feed for Ashok. Sun, 26 Apr 2026 00:21:41 +0100 https://buddypress.org/?v= en-US 30 hourly 2 99fc01400294463e2dea3d92de1142b9 Ashok replied to the topic How does genbin work? in the forum OSVVM https://osvvm.org/forums/topic/how-does-genbin-work#post-1929 Mon, 21 Feb 2022 21:06:55 +0000 Jim, Thanks very much. Wasn’t aware of all the documents available. Going through the documents to get better understanding.

]]> 0 ba5f188950a603e300c47e080a88150d Ashok started the topic How does genbin work? in the forum OSVVM https://osvvm.org/forums/topic/how-does-genbin-work Sat, 19 Feb 2022 23:41:06 +0000 Brand new to OSVVM. Familiar with SystemVerilog functional coverage language.

Here’s a sample code. Question follows the code.

library OSVVM;
use OSVVM.CoveragePkg.all;

architecture
signal op_code : std_logic_vector(2 downto 0);
signal mode : std_logic_vector(1 downto 0);
…
shared variable cp_opcode: CovPType;
shared variable…[Read more]

]]> 0 0d44fe11864fd4a5f5a075709b99da69 Ashok became a registered member https://osvvm.org/activity/p/6817 Fri, 22 Oct 2021 19:52:19 +0100 0