Open Source VHDL Verification Methodology | Cahit | Activity https://osvvm.org/members/cayt/activity Activity feed for Cahit. Sat, 23 May 2026 13:24:01 +0100 https://buddypress.org/?v= en-US 30 hourly 2 cc558fcbb166c12e03d6c5e332c7350b Cahit replied to the topic impore function GotScoreboards - Fatal: (SIGSEGV) Bad handle or reference. in the forum OSVVM https://osvvm.org/forums/topic/impore-function-gotscoreboards-fatal-sigsegv-bad-handle-or-reference#post-2569 Tue, 10 Sep 2024 07:51:35 +0100 Hi Jim,
That’s good to know. Thanks!

I did have issues running the osvvm demo as well, but luckyly my testbench is working – except the reporting part. We will be switching to a newer ModelSim version soon. I will try it out after the change.

Many thanks!
Cahit

]]> 0 8fe7609227398d062f5f1a54a142bd06 Cahit started the topic impore function GotScoreboards - Fatal: (SIGSEGV) Bad handle or reference. in the forum OSVVM https://osvvm.org/forums/topic/impore-function-gotscoreboards-fatal-sigsegv-bad-handle-or-reference Mon, 09 Sep 2024 10:15:05 +0100 Hi,

I am building a unit test for a large function that we use, but during report generation (EndOfTestReports) I get the following error.

# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 3 ns Iteration: 2 Process: /***_tb/test_ctrl_i/control_p File: /***/OsvvmLibraries/osvvm/ScoreboardGenericPkg.vhd
# Fatal error in Subprogram…[Read more]

]]> 0 a41aad7cbd311c9e72e190ae5b7af66d Cahit posted a new activity comment https://osvvm.org/archives/1594#comment-1656 Mon, 24 Feb 2020 07:13:25 +0000 Looking forward to it 🙂
Thanks Jim.

In reply to - Jim Lewis wrote a new post Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you […] ]]> d3391340bb77cf0409869fbf29fd9eb8 Cahit posted a new activity comment https://osvvm.org/archives/1594#comment-1654 Fri, 21 Feb 2020 15:35:07 +0000 I was wondering, if the webinar is recorded – and if yes, how to access it – for the OSVVM enthusiast, who unfortunately missed the event?

In reply to - Jim Lewis wrote a new post Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you […] ]]> 2049cac95a7996479904ee2eea4d4555 Cahit's profile was updated https://osvvm.org/activity/p/5137 Fri, 21 Feb 2020 13:59:13 +0000 0