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	<title>Open Source VHDL Verification Methodology | Charlie | Activity</title>
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				<title>Charlie started the topic Unique Requirement Pass Goals For Each Test Case in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/unique-requirement-pass-goals-for-each-test-case</link>
				<pubDate>Wed, 18 Jun 2025 10:58:26 +0100</pubDate>

									<content:encoded><![CDATA[<p>I have two separate test cases in my testbench &#8211; randomised_tests.vhd and directed_tests.vhd. I then have a separate checker module incorporating scoreboards and requirements tracking. Each of the requirements and their passed goals are declared inside the checker module, therefore the pass goals are common to both test cases.</p>
<p>I&#8217;m wondering if&hellip;<span class="activity-read-more" id="activity-read-more-10769"><a href="https://osvvm.org/forums/topic/unique-requirement-pass-goals-for-each-test-case" rel="nofollow ugc">[Read more]</a></span></p>
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				<title>Charlie became a registered member</title>
				<link>https://osvvm.org/activity/p/10729</link>
				<pubDate>Wed, 07 May 2025 10:03:03 +0100</pubDate>

				
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