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	<title>Open Source VHDL Verification Methodology | Chengshan | Activity</title>
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				<title>Chengshan replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/osvvm-2020-08-new-user-experience#post-1716</link>
				<pubDate>Sat, 19 Sep 2020 06:36:47 +0100</pubDate>

									<content:encoded><![CDATA[<p>#1 &#8211; If stopping the simulation with assertion or std.env.stop, it was not a &#8220;real&#8221; stop.<br />
Hitting the &#8220;run all&#8221; button in the simulator would let the test bench continue to run endlessly.<br />
Personally I don&#8217;t feel like this behavior.</p>
<p>Stopping the clock is the true end. When the simulator stops, there is nothing more to simulate.<br />
Hitting the &#8220;run&hellip;<span class="activity-read-more" id="activity-read-more-6097"><a href="https://osvvm.org/forums/topic/osvvm-2020-08-new-user-experience#post-1716" rel="nofollow ugc">[Read more]</a></span></p>
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				<title>Chengshan replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/osvvm-2020-08-new-user-experience#post-1715</link>
				<pubDate>Sat, 19 Sep 2020 06:01:04 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi Jim,</p>
<p>Thanks for the quick response.</p>
<p>#2 &#8211; Some learning experience here.<br />
I started the journey by studying the example test bench TbAxi4_BasicBurst.<br />
The example went broken as soon as I changed AXI_DATA_WIDTH to a wider one in TbAxi4.<br />
Looking back, it was probably the test cases.<br />
But at that time I did not realized that the test was doing&hellip;<span class="activity-read-more" id="activity-read-more-6096"><a href="https://osvvm.org/forums/topic/osvvm-2020-08-new-user-experience#post-1715" rel="nofollow ugc">[Read more]</a></span></p>
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				<title>Chengshan started the topic OSVVM 2020.08 New user experience in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/osvvm-2020-08-new-user-experience</link>
				<pubDate>Fri, 18 Sep 2020 20:08:34 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi I just created my very first OSVVM test bench based on the example.<br />
It was with release 2020.08.</p>
<p>Here are my experience/questions, mostly about the newly released AXI4 models:</p>
<p>1. Could the test bench be stopped gracefully by stopping all clocks?<br />
I don&#8217;t feel like the idea of using assertion or std.env.stop to end the simulation.<br />
Stopping the&hellip;<span class="activity-read-more" id="activity-read-more-6090"><a href="https://osvvm.org/forums/topic/osvvm-2020-08-new-user-experience" rel="nofollow ugc">[Read more]</a></span></p>
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				<title>Chengshan&#039;s profile was updated</title>
				<link>https://osvvm.org/activity/p/6089</link>
				<pubDate>Fri, 18 Sep 2020 19:16:10 +0100</pubDate>

				
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				<title>Chengshan became a registered member</title>
				<link>https://osvvm.org/activity/p/6078</link>
				<pubDate>Wed, 16 Sep 2020 03:48:40 +0100</pubDate>

				
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