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	<title>Open Source VHDL Verification Methodology | Barry Henderson | Activity</title>
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				<title>Barry Henderson replied to the topic failure to compile a Scoreboard in Modelsim DE using osvvm 2018.04 in the forum OSVVM</title>
				<link>https://osvvm.wpengine.com/forums/topic/failure-to-compile-a-scoreboard-in-modelsim-de-using-osvvm-2018-04/#post-1472</link>
				<pubDate>Wed, 01 Aug 2018 07:50:56 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi Jim, Many thanks for your answer. My problem is that i have tried every which way to get things to compile and i always get errors.My scoreboard generic package is defined like this now in a seperate design unit (i.e. a VHDL file):library IEEE;use IEEE.STD_LOGIC_1164.ALL;library osvvm;&#8211;use osvvm.OsvvmContext;use OSVVM.ScoreboardGenericPkg;use&hellip;<span class="activity-read-more" id="activity-read-more-5096"><a href="https://osvvm.wpengine.com/forums/topic/failure-to-compile-a-scoreboard-in-modelsim-de-using-osvvm-2018-04/#post-1472" rel="nofollow ugc">[Read more]</a></span></p>
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