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	<title>Open Source VHDL Verification Methodology | Edward Heim | Activity</title>
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				<title>Edward Heim replied to the topic Vivado simulator and OSVVM in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/vivado-simulator-and-osvvm#post-1841</link>
				<pubDate>Wed, 28 Jul 2021 05:06:04 +0100</pubDate>

									<content:encoded><![CDATA[<p>Thanks Jim. I appreciate the information. Initially I only need RandomPkg so I&#8217;ll try to compile the files myself.</p>
<p>Best regards, Edward</p>
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				<title>Edward Heim started the topic Vivado simulator and OSVVM in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/vivado-simulator-and-osvvm</link>
				<pubDate>Thu, 22 Jul 2021 00:27:44 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi</p>
<p>I&#8217;m trying to run a test bench that I&#8217;ve successfully run in Riviera in Vivado 2020.3. Even with the test bench compiled with VHDL 2008, the Vivado simulator doesn&#8217;t seem to support OSVVM packages. </p>
<p>Past posts that I&#8217;ve found on the forum re issues in Vivado are a few years old. Does anyone have updated experience?</p>
<p>Thanks, Edward</p>
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