Open Source VHDL Verification Methodology | Eilert Backhus | Activity https://osvvm.org/members/eilert/activity Activity feed for Eilert Backhus. Sat, 25 Jul 2026 11:33:59 +0100 https://buddypress.org/?v= en-US 30 hourly 2 99f2de0a56517e531ed78db7421ff6d1 Eilert Backhus replied to the topic VHDL port map between std_logic_vector(0 downto 0) and std_logic in the forum VHDL https://osvvm.org/forums/topic/vhdl-port-map-between-std_logic_vector0-downto-0-and-std_logic#post-2566 Thu, 05 Sep 2024 08:34:06 +0100 Hello Hassan.
It’s one of the fundamental concepts of VHDL: Strong Typing.

A vector is a different type than its base type.

You have mentioned a specific corner case: (0 downto 0)
As you mentioned this was the result of some generics, which means at some other time this vector could also result in e.g. (6 downto 0).

Now consider that your code…[Read more]

]]> 0 b6e3e610fb7b85ef35716e901723e57c Eilert Backhus replied to the topic RandomPkg: How to set weight for range in the forum OSVVM https://osvvm.wpengine.com/forums/topic/randompkg-how-to-set-weight-for-range/#post-1398 Thu, 29 Jun 2017 06:11:45 +0100 Hi Jim,I hoped that there’s some solution using the range notation like you showed:With named association, you can also do the following:
     A <= RndA.DistSlv((0=>5, 1 to 14 =>1, 15=>5), A'length) ;I just didn’t expect it to be so straight simple, since the defined type is self defined. You mentioned integer_vectors somewhere else. Are these…[Read more]

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