Open Source VHDL Verification Methodology | Markus | Activity https://osvvm.org/members/ferringerm/activity Activity feed for Markus. Sun, 26 Apr 2026 00:21:41 +0100 https://buddypress.org/?v= en-US 30 hourly 2 905bd0f915634441d808254c26d43b02 Markus replied to the topic Race conditions / buffer issues in console output in the forum OSVVM https://osvvm.org/forums/topic/race-conditions-buffer-issues-in-console-output#post-1978 Fri, 20 May 2022 06:16:30 +0100 It seems the problem was on my end after all
When I call
vsim -batch -do "build project.pro"
the output is fine. However, when I call it with a pipeline operator to postprocess the output
vsim -batch -do "build project.pro" | cat
the output is somehow mixed up.

This is a buffering problem which can be solved with unbuffer:
unbuffer -p vsim -batch…[Read more]

]]> 0 e4a028aead1b02082cff34f702249f04 Markus started the topic Race conditions / buffer issues in console output in the forum OSVVM https://osvvm.org/forums/topic/race-conditions-buffer-issues-in-console-output Fri, 20 May 2022 06:15:50 +0100 I had troubles concerning the order of console output, esp. in combination with ModelSim/Questasim.

Problem Description:
Assume the following proc in VendorScript_Mentor.tcl (pseudocode):
proc analyze {FileName} {
puts Starting VCOM
vcom ... $FileName
puts VCOM Done
}

I got the following output:
Starting VCOM
VCOM Done
…
<actual output…[Read more]

]]> 0 4850fd4e21fc7b6cc723d4756193efa7 Markus became a registered member https://osvvm.org/activity/p/6956 Fri, 03 Dec 2021 09:52:51 +0000 0