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	<title>Open Source VHDL Verification Methodology | Ian Gibbins | Activity</title>
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				<title>Ian Gibbins wrote a new post</title>
				<link>https://osvvm.org/?p=1628</link>
				<pubDate>Tue, 12 May 2020 06:18:58 +0100</pubDate>

									<content:encoded><![CDATA[<p>We are very pleased to post a real example OSVVM experience which has been shared by Miroslav Marinkovic.</p>
<p>Miroslav has made use of Functional coverage, Random test generation and Intelligent Coverage [&hellip;] <img loading="lazy" src="https://osvvm.wpenginepowered.com/wp-content/uploads/2020/04/tb-image.png" /></p>
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				<title>Ian Gibbins wrote a new post</title>
				<link>https://osvvm.org/?p=1602</link>
				<pubDate>Thu, 20 Feb 2020 13:53:21 +0000</pubDate>

									<content:encoded><![CDATA[<p>Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.</p>
<p>While your EDA vendor may [&hellip;] <img loading="lazy" src="https://osvvm.wpenginepowered.com/wp-content/uploads/2020/01/all-you-need-is-osvvm.jpeg" /></p>
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				<title>Ian Gibbins wrote a new post</title>
				<link>https://osvvm.org/?p=1601</link>
				<pubDate>Thu, 20 Feb 2020 13:46:22 +0000</pubDate>

									<content:encoded><![CDATA[<p>In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to Apache 2.0 license.  This is being done in p [&hellip;]</p>
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				<title>Ian Gibbins started the topic How to handle protected types in the forum VHDL</title>
				<link>https://osvvm.org/forums/topic/how-to-handle-protected-types</link>
				<pubDate>Tue, 03 Apr 2012 21:19:52 +0100</pubDate>

									<content:encoded><![CDATA[<p>I see that OS-VVM is using <em>protected types</em> internally at the quite advanced level. I have done my share of coding in VHDL but am not very familiar with this type of construct. Any suggestions how to improve my understanding?</p>
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