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	<title>Open Source VHDL Verification Methodology | kuri | Activity</title>
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				<title>kuri started the topic About cyclic randomlike the randc of SystemVerilog in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/about-cyclic-randomlike-the-randc-of-systemverilog</link>
				<pubDate>Tue, 17 Apr 2012 09:59:04 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi,Can the cyclic random like the randc of SystemVerilog be described in OS-VVM?I think that I describe it by using the function coverage and RandCovPoint method.Is this idea correct?best regards,kuri</p>
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