Open Source VHDL Verification Methodology | Mikael | Activity https://osvvm.org/members/mickedykare/activity Activity feed for Mikael. Sun, 26 Apr 2026 00:21:41 +0100 https://buddypress.org/?v= en-US 30 hourly 2 0bf9a0133e18484cd3ccfff2ff7079b3 Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM https://osvvm.org/forums/topic/safer-check-if-simulation-passed-or-not#post-2787 Wed, 15 Oct 2025 07:53:49 +0100 The Report APIs should be there in Questa sim 2025.2.
The latest Questasim version is now 2025.3

Remember that today, mixed language designs are very common. Some IPs are only available in Verilog.
So it is not just VHDL assertions that can be a source of errors.
There could be SVA assertions, both immediate and concurrent.

IPs or library…[Read more]

]]> 0 4509a91584be8ad2fa78a118ddee294a Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM https://osvvm.org/forums/topic/safer-check-if-simulation-passed-or-not#post-2785 Tue, 14 Oct 2025 08:50:22 +0100 By saving the UCDB file for each testcase (<testname>.ucdb , you can also check the teststatus afterwards:

>vcover attribute OsvvmTemp_Questa/TbAxi4_DemoMemoryReadWrite1.ucdb

The tcl procedure I use to check the test status,just contact me and I will send it. Seems like the code is blocked.

]]> 0 90854e07a6c7ae7906a7532561105c6c Mikael started the topic Safer Check if Simulation passed or Not in the forum OSVVM https://osvvm.org/forums/topic/safer-check-if-simulation-passed-or-not Tue, 14 Oct 2025 08:48:25 +0100 Today the outcome of the simulation is solely dependent on the OSVVM report server and if you have triggered an error or not.
But if you have for example an external library cell/ip that uses assertions, it can still look as the simulation passed while it indeed failed.

I added “assert false” in a testcase to illustrate the problem. This is the…[Read more]

]]> 0 4495f70f165550ea9f67ea6b5930e64f Mikael became a registered member https://osvvm.org/activity/p/10873 Tue, 14 Oct 2025 00:07:41 +0100 0