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	<title>Open Source VHDL Verification Methodology | Narayanan | Activity</title>
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				<title>Narayanan started the topic Which Transactor to use Stream or Address in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/which-transactor-to-use-stream-or-address</link>
				<pubDate>Tue, 07 May 2024 16:44:13 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hello, I have a simple ALU DUT which I using to learn OSVVM. The ALU requires 3 inputs (operation, src1, src2). If I wanted to use the Stream Model Transactor how should I use the StreamRecType.</p>
<p>a) Pack the 3 inputs into a std_logic_vector_max_c via DataToModel<br />
b) Modify/Create new StreamRecType<br />
c) Other?</p>
<p>Regards,<br />
Ryan</p>
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				<title>Narayanan became a registered member</title>
				<link>https://osvvm.org/activity/p/9780</link>
				<pubDate>Thu, 06 Jul 2023 19:40:26 +0100</pubDate>

				
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