Open Source VHDL Verification Methodology | Remy | Activity https://osvvm.org/members/remy/activity Activity feed for Remy. Sat, 30 May 2026 21:48:28 +0100 https://buddypress.org/?v= en-US 30 hourly 2 f6f928c003d238321080f4d8a8b5652f Remy replied to the topic Vivado : Error with AXI Data width in the forum OSVVM https://osvvm.org/forums/topic/vivado-error-with-axi-data-width#post-2798 Thu, 30 Oct 2025 14:46:33 +0000 Hi Jim,
I tested the same test case with Questasim, and I’m not seeing the same issues.

Regards,
Remy

]]> 0 342789a1bea53986d42e0009b574bc96 Remy replied to the topic Vivado : Error with AXI Data width in the forum OSVVM https://osvvm.org/forums/topic/vivado-error-with-axi-data-width#post-2797 Tue, 28 Oct 2025 07:50:57 +0000 Hi Jim,
I updated the AXI FULL OSVVM testbench available here.


architecture TestHarness of TbAxi4 is
constant AXI_ADDR_WIDTH : integer := 16 ;
constant AXI_DATA_WIDTH : integer := 256 ;
constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ;

I modified the width of AXI DATA and AXI ADDR, and adapted the test cases to include the new…[Read more]

]]> 0 3208a0f7a0f04e0a480f033859355a86 Remy started the topic Vivado : Error with AXI Data width in the forum OSVVM https://osvvm.org/forums/topic/vivado-error-with-axi-data-width Mon, 27 Oct 2025 16:24:00 +0000 Hello,
I am using OSVVM 2025 with Vivado 2025.1.1.
I started from the AXI example.
When I change the values of AXI_ADDR_WIDTH to 16 and AXI_DATA_WIDTH to 256, the signals sWData, sWValid, and sWReady become undefined.
Is this bug dependent on Vivado or AXI drivers?

]]> 0 765b98557acd07cfb3cc5a3fa7ad4ae8 Remy became a registered member https://osvvm.org/activity/p/10871 Mon, 13 Oct 2025 11:18:28 +0100 0