Srinivasan Venkataramanan
Forum Replies Created
-
AuthorPosts
-
January 6, 2016 at 09:13 #1092
*Is there a working version for CDN IUS finally please? I haven’t tried but am interested in doing so, given that we have a poster on this topic at DVCon USA 2016.
Thanks
Srini
January 6, 2016 at 09:11 #1091*You may be able to compile it yourself using the steps given in the following blog: https://veriflabs.com/2016/01/using-latest-osvvm-with-questa-10-4/ (Though for latest release, idea should be common). In case you are stuck at more issues, post error message here.
Good Luck
Srini
June 13, 2014 at 11:03 #816*
Steve,
Can you confirm if this issue is still open and if yes, which VCS-MX version?
Regards
Srini
May 28, 2013 at 13:36 #646*Jim,
I’m not an expert in UCIS (yet, maybe in future) – but yes, you got my thought correctly: From OS-VVM lib if we can generate vendor independent UCIS DB that would be awesome. I know it is a long shot, perhaps by 2020 (joking), but more realistically – it is one internship project for a smart graduate student I guess.
Meanwhile vendors like Aldec might take the lead and do it in their tool sooner.
Srini
May 23, 2013 at 20:12 #627May 23, 2013 at 20:04 #626*Jim,
Not sure if I fully understood your problem, but to me it looks like you need a “custom” OSVVM lib while testing release candidates than the tool’s built-in version. If yes, how about simply asking tool to point to your dir? In case of Riviera-Pro for instance:
osvvm = “../Jim_LATEST_OSVVM//osvvm.lib”
Then you could use vcom -work osvvm <os_vmm_src.vhdl>
Or maybe I am missing something in your problem statement?
Srini
May 14, 2013 at 10:35 #614*Jerry/Jim,
A rather generic, non-technical remark/observation – this forum is hard to locate from the front/landing page of osvvm.org – it is there as a small link at the bottom of front page.
How about adding it as a menu item/toolbar – similar to the other links (see below).
Thanks
Srini
May 14, 2013 at 08:29 #612* I also noticed that the FIFO example uses:
<code>
use work.RandomBasePkg.all ;
</code>
I believe something like this is far better approach:
<code>
library osvvm;
use osvvm.RandomBasePkg.all ;
</code>
Questa 10.2 actually ships OSVVM precompiled and the above change makes it work out of the box (no need to recompile the OSVVM sources, though one could say we use -incr flow).
Any comments?
Also - has anyone tried this on IUS 12.2 release from Cadence? That's our next step at CVC, will update here on our findings soon.
If we do agree the above fix is useful, how do we submit the changes/contributions to the examples?
Regards
Srini
www.cvcblr.com/blog
May 10, 2013 at 05:21 #609My views on PSL vs. SVA for VHDL users:
1. PSL is more intuitive choice here as it has VHDL flavor (now that’s part of VHDL 2008). Hence both RTL and Verif team can add 9and debug) assertions. This is very important from a methodology standpoint of adopting ABV.
2. PSL historically has better support in Formal tools than SVA
3. PSL has some nice inheritance features that SVA (not SV-TB/class stuff) doesn’t have
4. PSL’s so called FL (Foundation Layer/language) sub-set is lot more efficient and intuitive to write succinct temporals than SEREs/sequences as in SVA (2005). Note: SVA-09 did add it and calls it LTL, but very few tools support it even today. So if you want to be productive PSL is THE way to go. See: https://www.cvcblr.com/blog/?p=689 for a small example on this.
5. PSL also has SV flavor, so learn one language, both VHDL & SV users can use it.
6. PSL works with E/Specman nicely with built-in action blocks (similar to Jim’s proposals), so this makes it even more compelling.
7. Last but not the least – it is not all that difficult to migrate from PSL to SVA (or vice versa) if one needs in the future, so get productive with PSL today and if you ever have to migrate to SVA – it is not that hard.
Good Luck
Srini
-
AuthorPosts