I have two main goals with this test bench:

– Check that pixel values generated on the sensor input appear in the appropriate form on the AXI-Stream output, and completion interrupts and status registers are set correctly
– Check that the interface logic is well-behaved in the case of errors on the LVDS inputs, i.e., no FSM…[Read more]

thanks, I appreciate your detailed response. I have started implementing the VC with most parameters as model options. Originally I wanted to create a custom transaction type, but for now I am using the Stream MIT. I use the data parameter of Send() to pass the seed for pixel-data generation and generate a complete frame. This doesn’t…[Read more]

we’re currently looking for a verification methodology to integrate into our VHDL-based FPGA flow. I’m interested in how to create stimulus for custom chip interfaces, in this case an image sensor with a proprietary serial interface with multiple LVDS lanes. The interface module translates the LVDS input into an AXI-Stream packet with video…[Read more]