Open Source VHDL Verification Methodology | Steve Chan | Activity https://osvvm.org/members/ychan/activity Activity feed for Steve Chan. Sat, 18 Jul 2026 10:54:38 +0100 https://buddypress.org/?v= en-US 30 hourly 2 e54a7704346b3aee7efeb6563c476494 Steve Chan started the topic PSL or SVA? in the forum VHDL https://osvvm.org/forums/topic/psl-or-sva Fri, 01 Feb 2013 17:23:23 +0000 *Hi allI am planning to start embedding the more advance assertion contruct in my HDL/TestBench design.My company is generally a VHDL house, but I can foresee use of SV in the future.A mixed language environment is very likely to happen (as a matter it already exist)I have read either PSL or SVA can work in both SV and VHDL.So which assertion…[Read more]

]]> 0 1129ffbd61f029e7471fcc890ffa6165 Steve Chan started the topic How to compare compare std_logic and integer in the forum VHDL https://osvvm.org/forums/topic/how-to-compare-compare-std_logic-and-integer Fri, 19 Oct 2012 19:46:22 +0100 Hi expertA supposing easy question.How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?I was trying to find use assert to compare the std_logic and the input vector in integer.Thanks  

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