Open Source VHDL Verification Methodology | Ajeetha Kumari | Activity https://osvvm.org/members/ajeetha/activity Activity feed for Ajeetha Kumari. Sun, 24 May 2026 23:35:46 +0100 https://buddypress.org/?v= en-US 30 hourly 2 cf8d9aa1031ce916b32c605547d2c82a Ajeetha Kumari started the topic Using TCover to model bit transitions in the forum OSVVM https://osvvm.org/forums/topic/using-tcover-to-model-bit-transitions Wed, 12 Mar 2025 14:58:02 +0000 I am adding support for bit vector functional/toggle coverage using OSVVM. I have basic every-bit cover working (Will be glad to share a prototype if anyone is willing to review). Now, the next step is to ensure each bit really transitioned from 0 to 1 and 1 to 0. I tried using TCover and by reading the implementation it looks like it would…[Read more]

]]> 0 75746b19636fbe4d2d886976c1907750 Ajeetha Kumari started the topic SBRD: Check API uses AffirmIf, why GetAffirmCount is 0? in the forum OSVVM https://osvvm.org/forums/topic/sbrd-check-api-uses-affirmif-why-getaffirmcount-is-0 Fri, 07 Jun 2024 20:54:09 +0100 SBRD User guide says:
<quote>
Check a received value (ActualType) with value in scoreboard. The Match function is
used to determine if the received and expected values match. Checking is handled by
AffirmIf. As a result, if they match a log PASSED is generated, otherwise, an alert
ERROR is generated.
</quote>

I didn’t create any AlertID (yet),…[Read more]

]]> 0 0eea3d3713a427d42df0046ad5c8dd5d Ajeetha Kumari replied to the topic SBRD package issue with Modelsim FPGA edition in the forum OSVVM https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition#post-2491 Fri, 07 Jun 2024 20:27:24 +0100 That worked, thanks. Can we bukcteize this as potential race condition?

]]> 0 d4735fdf076d12a105c2d8ac1afdd153 Ajeetha Kumari replied to the topic SBRD package issue with Modelsim FPGA edition in the forum OSVVM https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition#post-2488 Fri, 07 Jun 2024 17:11:58 +0100 I guessed that and did add a 1ns delay before calling NewID – please see the stim process above. Still no luck!

Thanks

]]> 0 c99480edee97a50c21816c2e918f34f7 Ajeetha Kumari started the topic SBRD package issue with Modelsim FPGA edition in the forum OSVVM https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition Fri, 07 Jun 2024 08:25:32 +0100 Thanks Jim for the help with MTI version check (18.1 produces a seg-fault with NewID call). Now I have updated to the latest available – 20.1 and I see that seg-fault is resolved. However, during push I get:

<log>
# Time: 1 ns Iteration: 0 Instance: /tb_af_up_dn_counter/u_testcase
# %% Alert FAILURE in OSVVM, Scoreboard Push Index:…[Read more]

]]> 0 e45d1eb82a12264dae487c4bc7d31b41 Ajeetha Kumari replied to the topic Generic testControlProc - can this be a pattern? in the forum OSVVM https://osvvm.org/forums/topic/generic-testcontrolproc-can-this-be-a-pattern#post-2485 Fri, 07 Jun 2024 08:21:53 +0100 Thanks, aligns with my thoughts. Yes the generator already creates/uses clock/reset procedures.

Regards
Ajeetha

]]> 0 edc422f555cda9ca5129780ec0e1d911 Ajeetha Kumari changed their profile picture https://osvvm.org/activity/p/10227 Thu, 06 Jun 2024 06:45:06 +0100 0 c716f398ee506667844046817c670c51 Ajeetha Kumari's profile was updated https://osvvm.org/activity/p/10226 Thu, 06 Jun 2024 06:39:40 +0100 0 8724c8e3d966b0dc1dc7b3b24ef6c6f8 Ajeetha Kumari started the topic Generic testControlProc - can this be a pattern? in the forum OSVVM https://osvvm.org/forums/topic/generic-testcontrolproc-can-this-be-a-pattern Thu, 06 Jun 2024 06:13:57 +0100 Hi there,
Coming from SV/UVM and the concept of design patterns applied to testbenches, am looking for common patterns in a typical OSVVM TB. Things such as:

1. ClockGen
2. ResetGen
3. EndOfTestReport

I believe the above 3 are straightforward (need to add #3 to my generator yet). What about some of the initialization code that I see in TbUart…[Read more]

]]> 0 7c0a946d80f2a0dad71bc4de7ce13f7c Ajeetha Kumari replied to the topic GHDL workarounds - any known ones? in the forum OSVVM https://osvvm.org/forums/topic/ghdl-workarounds-any-known-ones#post-2475 Thu, 06 Jun 2024 06:07:52 +0100 Thanks Jim, I understand this better now – it’s scoping issue when multiple types are getting visible to a test.

Regards
Ajeetha

]]> 0 e21a89e961a94b9dbad619cef8ed06b5 Ajeetha Kumari started the topic GHDL workarounds - any known ones? in the forum OSVVM https://osvvm.org/forums/topic/ghdl-workarounds-any-known-ones Wed, 05 Jun 2024 17:02:24 +0100 I am new here in this forum, am creating a Python based utility to enhance productivity with OSVVM based TBs. One of them is a testbench skeleton generator that should go live shortly (opensource). While navigating some examples I see:

[code]
library OSVVM ;
context OSVVM.OsvvmContext ;
— use osvvm.ScoreboardPkg_slv.all ;
–!! GHDL
use…[Read more]

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