SBRD package issue with Modelsim FPGA edition

[Ajeetha Kumari]

Thanks Jim for the help with MTI version check (18.1 produces a seg-fault with NewID call). Now I have updated to the latest available – 20.1 and I see that seg-fault is resolved. However, during push I get:

<log>
# Time: 1 ns Iteration: 0 Instance: /tb_af_up_dn_counter/u_testcase
# %% Alert FAILURE in OSVVM, Scoreboard Push Index: -2147483648is not in the range (1to 1) at 1 ns
#
</log>

My code looks like:

signal SB_int : osvvm.ScoreboardPkg_int.ScoreBoardIDType;
begin

stim : process
begin
wait for 1 ns;
SB_int <= NewID("COUNT_SB");
report ("SB_int: " & integer'image(SB_int.Id));
i_up_or_down <= '0';
push(SB_int, 2);

Looks like the NewID returns a crazy number?

Thanks
Ajeetha

[Jim Lewis]

Hi Ajeetha,
Nope. That is integer’left.

Put a “wait for 0 ns” before reading the signal. That allows a simulation cycle to go by and the signal to update to the value assigned by NewID.

Jim

[Ajeetha Kumari]

I guessed that and did add a 1ns delay before calling NewID – please see the stim process above. Still no luck!

Thanks

[Jim Lewis]

Do the following. The wait for 0 ns follows the assignment to SB_int to allow SB_int to update.

stim : process
begin
  SB_int <= NewID("COUNT_SB");
  wait for 0 ns;  -- let SB_int to update
  report ("SB_int: " & integer'image(SB_int.Id));
  i_up_or_down <= '0';
  push(SB_int, 2);
  . . . 

[Ajeetha Kumari]

That worked, thanks. Can we bukcteize this as potential race condition?

[Jim Lewis]

This is just the VHDL signal use model when reading it after assigning it in a process. Since RTL does not allow wait for 0 ns, it is limited to testbenches.

Verilog assignments have the same sort of issue.

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