Open Source VHDL Verification Methodology | Andrea | Activity https://osvvm.org/members/andrea-foradori/activity Activity feed for Andrea. Mon, 25 May 2026 07:33:49 +0100 https://buddypress.org/?v= en-US 30 hourly 2 4458673c7b1f65cdad89531020c2b71d Andrea started the topic Question to the OSVVM community: how to approach the methodology, learning curve in the forum OSVVM https://osvvm.org/forums/topic/question-to-the-osvvm-community-how-to-approach-the-methodology-learning-curve Fri, 27 Mar 2020 14:35:13 +0000 Hello all,

I am new with OSVVM and I’d have some questions about the learning curve time and other details to consider.
In my past experience I worked as VHDL developer, so the reason why I would like to use OSVVM is that I do not want to learn SystemVerilog (for UVM). Second, in my current company there are few people that work as FW engineer…[Read more]

]]> 0 e78b487b89b704ea3265dd8463ce2082 Andrea became a registered member https://osvvm.org/activity/p/5187 Thu, 12 Mar 2020 14:11:11 +0000 0