`
$ rlwrap -c tclsh
$ source ../OsvvmLibraries/Scripts/StartUp.tcl
OSVVM Script Version: 2025.02
Simulator Version: GHDL-5.0.0-dev
`

For the former, just to be clear, , I have an AxiStreamReceiver and I am testing my DUT which has an axis master. So, I want to assert in the TestCase tready before tvalid or after tvalid (1, 2, n clock cycles). Is that what you meant? Is there any example to follow?

Thank you for the clear answer. Makes total sense to skip the post-synthesis simulation then for my purpose. I am in fact using the OSVVM AXI Stream components which have tpd. I have a design with mainly several axi streams, so I am following the testcase OsvvmLibraries/AXI4/AxiStream/TestCases/TbStream_SendGetDemo1.vhd.

I need to…[Read more]

I am getting the same results in behavioral simulation in vivado and also in GHDL. As I want to be sure that post-synthesis works without generating a bitstream (which…[Read more]

Is there any specific reason? Is it possible to set at the beginning of the process whether tready should be 1 or 0?

Are there any updates on this?

I am also looking to not having tready asserted by the receiver at the beginning, but instead using RECEIVE_READY_BEFORE_VALID=FALSE and RECEIVE_READY_DELAY_CYCLES to assert tready after tvalid is asserted. See here https://ibb.co/jZVyy9ZH
Thank you.

ps: Do you have a new and updated documentation for the…[Read more]

Are there any updates on this?

I am also looking to not having tready asserted by the receiver at the beginning, but instead using RECEIVE_READY_BEFORE_VALID=FALSE and RECEIVE_READY_DELAY_CYCLES to assert tready after tvalid is asserted.

Thank you.

What about running the simulation in vivado? I’m mostly interested in post synthesis functional simulation as I have a vhdl module currently that works fine in behavioral simulation and works…[Read more]