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	<title>Open Source VHDL Verification Methodology | Miroslav Marinkovic | Activity</title>
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				<title>Miroslav Marinkovic replied to the topic AlertLogPkg (OSVVM 2020.08) in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/alertlogpkg-osvvm-2020-08#post-1748</link>
				<pubDate>Mon, 30 Nov 2020 09:14:13 +0000</pubDate>

									<content:encoded><![CDATA[<p>Hi Stefen,</p>
<p>Regarding topic 2) I think there is a problem with that specific version Questa/ModelSim 2019.2, but I don´t know exactly a reason.<br />
Try another version (previous or later).</p>
<p>Best,<br />
Miroslav</p>
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				<title>Miroslav Marinkovic posted a new activity comment</title>
				<link>https://osvvm.org/archives/1661#comment-1664</link>
				<pubDate>Fri, 19 Jun 2020 13:30:58 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi David,</p>
<p>Thanks for nice post, it is quite useful.</p>
<p>I have a few comments:<br />
1.  If we want fewer lines of the code, we can combine Bins using concatenation &amp;, for example :</p>
<p>&#8212; Test21<br />
FSM_CP.AddCross(&#8220;Test21&#8221;, GenBin(BlackJack_type&#8217;POS(Test21)),<br />
GenBin(BlackJack_type&#8217;POS(BustState)) &amp; GenBin(BlackJack_type&#8217;POS(HoldState)) &amp;&hellip;<span class="activity-read-more" id="activity-read-more-5561"><a href="https://osvvm.org/archives/1661#comment-1664" rel="nofollow ugc">[Read more]</a></span></p>
				<strong>In reply to</strong> -
				<a href="https://osvvm.org/members/dcfeda" rel="nofollow ugc">David Clift</a> wrote a new post In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an [&hellip;]			]]></content:encoded>
				
				
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				<title>Miroslav Marinkovic replied to the topic Question to the OSVVM community: how to approach the methodology, learning curve in the forum OSVVM</title>
				<link>https://osvvm.org/forums/topic/question-to-the-osvvm-community-how-to-approach-the-methodology-learning-curve#post-1625</link>
				<pubDate>Thu, 02 Apr 2020 12:28:20 +0100</pubDate>

									<content:encoded><![CDATA[<p>Hi Andrea,</p>
<p>Regarding your question 3):</p>
<p>First, you mentioned that your current VHDL testbenches write output data into a file, and then you process (offline) the obtained data vs. reference data.<br />
In my opinion, it is better to compare output data vs. reference data directly in VHDL testbench, because you have a self-checking testbench in that&hellip;<span class="activity-read-more" id="activity-read-more-5235"><a href="https://osvvm.org/forums/topic/question-to-the-osvvm-community-how-to-approach-the-methodology-learning-curve#post-1625" rel="nofollow ugc">[Read more]</a></span></p>
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