Open Source VHDL Verification Methodology | Oliver | Activity https://osvvm.org/members/oliver/activity Activity feed for Oliver. Wed, 10 Jun 2026 17:53:02 +0100 https://buddypress.org/?v= en-US 30 hourly 2 1dd6e38de9aa66aff2bdc106fca15dd1 Oliver started the topic Xilinx not supporting VHDL anymore? in the forum VHDL https://osvvm.org/forums/topic/xilinx-not-supporting-vhdl-anymore Thu, 27 Apr 2023 12:15:32 +0100 I wonder if / why Xilinx doesn’t support VHDL anymore:
In the Feb 16, 2023 Xilinx document 63988 – “How to run timing simulation using Vivado Simulator?” it is stated: “There is no support for VHDL timing simulation.”
And in the Feb 16, 2023 Xilinx article “Simulating AXI interfaces with the AXI Verification IP (AXI VIP)” it says that “All of the…[Read more]

]]> 0 a8094dc7c74472d03582c094aae7835e Oliver replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM https://osvvm.org/forums/topic/verification-with-systemverilog-or-vhdl#post-2144 Thu, 26 Jan 2023 10:11:43 +0000 Hi Jim,
thanks for the link. Now that I finally got my tools working I will have a look at it soon. The OSVVM demo tests look good and run well (not when following the old user’s guide in the OSVVM Examples zip archive on this site though). Unfortunately the simulation of Xilinx PCIe-demo-design with Vivado will not run when the language is set to…[Read more]

]]> 0 22419b922de1c951f258d075573f14c9 Oliver replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM https://osvvm.org/forums/topic/verification-with-systemverilog-or-vhdl#post-2114 Mon, 05 Dec 2022 14:11:09 +0000 Hi Jim,

thank you for the detailed answers!

Actually I’m looking at the PCIe test framework from Xilinx. The AXI I’m planning to verify is already included in OSVVM, as I could see. For QSPI as another task I will probably need to write my own.

Best regards
Oliver

]]> 0 4858506c3ed8c1861538039ad5fda870 Oliver started the topic Verification with SystemVerilog or VHDL in the forum OSVVM https://osvvm.org/forums/topic/verification-with-systemverilog-or-vhdl Fri, 02 Dec 2022 09:49:05 +0000 Hello,
regarding OSVVM for verification of FPGA design I have a question.
My colleague told me, that we need to use SystemVerilog instead of VHDL for a new project. The problem he sees is that Xilinx provides the cores in Verilog and the test framework in System-VL. Only this is automatically built and provided by the demo. If we wanted to take…[Read more]

]]> 0 fd66e6e5012f9cfae7b79a2c64ff37ad Oliver became a registered member https://osvvm.org/activity/p/9020 Fri, 25 Nov 2022 22:36:28 +0000 0