Xilinx not supporting VHDL anymore?

[Oliver]

I wonder if / why Xilinx doesn’t support VHDL anymore:
In the Feb 16, 2023 Xilinx document 63988 – “How to run timing simulation using Vivado Simulator?” it is stated: “There is no support for VHDL timing simulation.”
And in the Feb 16, 2023 Xilinx article “Simulating AXI interfaces with the AXI Verification IP (AXI VIP)” it says that “All of the test bench files are written in SystemVerilog. To enjoy all of the features of the AXI VIP, this IP should be included in a SystemVerilog test bench.”
How about the other vendors?
And how can I integrate these with OSVVM?

[Iztok]

Vivado 2022.2 simulator states to supports VHDL-2008. While this is meant to mean full support, there certainly are still many issues present. The focus was probably to support language features already supported in synthesis.

I personally tested support for VHDL-2008 fixed point number libraries, which require generic packages.

Vivado 2023.1 added VHDL-2019 support to synthesis, but not to simulation.

The Xilinx support article you mentioned discusses timing annotated netlist simulation, which is something rarely done, especially for FPGA development, it is a bit more common in ASIC development (for power estimation signal toggling waveforms). The Verilog code here is the netlist. Since this simulation is very slow, it is usually limited to few tests, so not to much effort for the user to maintain some Verilog code.

[fpgaphreak]

I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.

Xilinx disreagards the fact that VHDL has certain advantages over Verilog and is the preferred HDL in Europe.

[Hassan]

“A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.”. What does this really mean that it cannot be build with AXI-Interface in VHDL? AXI interface is just bunch of signals and the design will eventually get mapped to FPGA pins and compiled to get netlist and bitstream. Why should VHDL AXI interface cause problem in that?

[Author]

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