Open Source VHDL Verification Methodology | Per | Activity https://osvvm.org/members/orkaboy/activity Activity feed for Per. Sun, 14 Jun 2026 12:19:30 +0100 https://buddypress.org/?v= en-US 30 hourly 2 24b336c2174f2949d5fef9a261bc22b8 Per replied to the topic Expected failures in custom VC based on AddressBusRecType in the forum OSVVM https://osvvm.org/forums/topic/expected-failures-in-custom-vc-based-on-addressbusrectype#post-2049 Tue, 09 Aug 2022 07:16:00 +0100 Hello, thanks for your response!

Inspired by this I ended up using GetModelOptions to implement checking for slave error (my VC is a Wishbone master), and this appears to work as intended:


-- Test invalid register in slave (raise slave error)
ReadCheck(TransRec, x"100FF", x"0000");
GetModelOptions(TransRec, WISHBONE_OPT_ERR,…[Read more]

]]> 0 f152da8fbf0e79cf4800b270b70b6f26 Per started the topic Expected failures in custom VC based on AddressBusRecType in the forum OSVVM https://osvvm.org/forums/topic/expected-failures-in-custom-vc-based-on-addressbusrectype Thu, 04 Aug 2022 06:00:07 +0100 Hi! I’ve recently started using OSVVM for my HDL designs, and haven’t fully learned how the system works yet.

What I’m trying to do is implement a Wishbone VC based on AddressBusRecType (this probably already exists somewhere, but there are other VCs I need to implement, so I rather learn the method), and I want to implement detecting failures…[Read more]

]]> 0 22a0b4d5aaa4e2b877d48037ed5cc9a5 Per became a registered member https://osvvm.org/activity/p/8504 Wed, 03 Aug 2022 08:58:34 +0100 0