Expected failures in custom VC based on AddressBusRecType
August 4, 2022 at 07:00 #2038PerMember
Hi! I’ve recently started using OSVVM for my HDL designs, and haven’t fully learned how the system works yet.
What I’m trying to do is implement a Wishbone VC based on AddressBusRecType (this probably already exists somewhere, but there are other VCs I need to implement, so I rather learn the method), and I want to implement detecting failures (the WB_ERR and WB_RTY signals for slave error/retry respectively). Basically, I want to add some property to my Read/Write calls in the test suite where I’m expecting the call to fail due to a bus error.
Looking through the OsvvmLibraries examples, I found something similar implemented for the UartTx/Rx VCs. These use the ParamTo/FromModel fields in StreamRecType to communicate various forms of errors. I thought I’d do the same, but from what I can tell, the Param fields are not present on the AddressBusRecType. I assume the AXI VCs implement errors in some way, but I’m not familiar enough with the code to find where.
TLDR, my question is this: How can one best implement bus error signaling when creating a VC based on AddressBusRecType?August 8, 2022 at 14:29 #2042Jim LewisMember
As you have noted, unlike StreamRecType, AddressBusRecType does not have a params field.
What I do in the Axi4Manager VC is use SetModelOptions to set an WB_ERR expected and a WB_RTY expected – sometimes coded together, sometimes coded separately. The AXI4 response codes that need to be checked are BRESP and RRESP. The way we check those is:
-- Write transfer that expects a SLVERR SetAxi4Options(ManagerRec, BRESP, SLVERR) ; Write(ManagerRec, X"0002_0000", X"0002_0101" ) ; SetAxi4Options(ManagerRec, BRESP, OKAY) ; -- Read transfer that expects a SLVERR SetAxi4Options(ManagerRec, RRESP, SLVERR) ; Read(ManagerRec, X"0004_000C", Data) ; AffirmIfEqual(Data, X"0004_0404", "Manager Read Data: ") ; SetAxi4Options(ManagerRec, RRESP, OKAY) ;
The AddressBus MIT SetModelOptions requires that the values BRESP and RRESP be integer values. Which if you create BRESP and RRESP as integer constants you can easily do. I prefer to use ENUMS instead, so I created SetAxi4Options to do the call:
SetModelOptions(ManagerRec, Axi4OptionsType'POS(BRESP), Axi4RespEnumType'pos(OKAY)) ;
SetAxi4Options is in the package AXI4/common/src/Axi4OptionsPkg.vhd.
StreamRecType has the params field because many streaming interfaces need either error codes or additional information to do every transaction. Long term AddressBusRecType may need this capability too if there is side-band information other than Address and Data that needs to be specified on every call.
JimAugust 9, 2022 at 08:16 #2049PerMember
Hello, thanks for your response!
Inspired by this I ended up using GetModelOptions to implement checking for slave error (my VC is a Wishbone master), and this appears to work as intended:
-- Test invalid register in slave (raise slave error) ReadCheck(TransRec, x"100FF", x"0000"); GetModelOptions(TransRec, WISHBONE_OPT_ERR, BoolOpt); AffirmIfEqual(BoolOpt, TRUE, "Expected slave error: ");
And in the VC:
when GET_MODEL_OPTIONS => case TransRec.Options is when WISHBONE_OPT_ERR => TransRec.BoolFromModel <= ??wbm_i.wb_err; -- VHDL-2008 operator to convert std_logic to boolean when others => null; end case;
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