Open Source VHDL Verification Methodology | David Clift | Activity https://osvvm.org/members/dcfeda/activity Activity feed for David Clift. Wed, 15 Apr 2026 14:48:28 +0100 https://buddypress.org/?v= en-US 30 hourly 2 1514fda45da4cb99f332ef84bb660eda David Clift replied to the topic At the end of the simulation, AlertLogPkg.vhd must open. causes error message. in the forum OSVVM https://osvvm.org/forums/topic/at-the-end-of-the-simulation-alertlogpkg-vhd-must-open-causes-error-message#post-2374 Wed, 24 Apr 2024 15:56:58 +0100 Hi Jeremy,

If you are using Riviera-PRO, you can stop the GUI from opening the terminating VHDL file by unsettling “Open editor when simulation is interrupted from source code.” You will find this in Tools –>Preference under Debug–>General.

I hope this helps.
Regards
David…

]]> 0 ab2615c53f00994d812794a9a57d7027 David Clift replied to the topic OSVVM in DO-254 DAL A-B in the forum OSVVM https://osvvm.org/forums/topic/osvvm-in-do-254-dal-a-b#post-1944 Wed, 16 Mar 2022 10:29:57 +0000 Hi Daniel,

Thank you for your post. Whilst I agree that in general UVM is the number one verification framework for ASICS and FPGAs as seen in the 2020 Wilson research surveys. These statistics do not tell the full story as these results are across all industry segments. For DO-254 designs, we still see VHDL as the number one testbench language,…[Read more]

]]> 0 37a84936ef2ac7e571d8b52d0bb767ef David Clift posted a new activity comment https://osvvm.org/archives/1661#comment-1665 Thu, 25 Jun 2020 10:11:54 +0100 Hi Miroslav,
Thank you for your kind comments and encouragement, I am glad my post was helpful, hopefully you will find my upcoming post useful as well.
With regards to your questions:
1. Could you use concatenation to shorten the code? Probably, I haven’t tried it. Typically I tend to write things out longhand so to speak, as you see here each…[Read more]

In reply to - David Clift wrote a new post In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an […] ]]> 250045a90ac97af3a42570b665992f20 David Clift wrote a new post https://osvvm.org/?p=1661 Fri, 12 Jun 2020 13:52:18 +0100 In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage […]

]]> 2 f25ca58a87a550e56bddfb888537d74f David Clift wrote a new post https://osvvm.org/?p=1643 Tue, 19 May 2020 16:01:56 +0100 There are many things that differentiate VHDL from Verilog. One example, is the ability to use global signals in Verilog, which enables a signal at the top-level to connect to one or more points in the hierarchy. […]

]]> 0 d895f575f3817ffa691aa00a8f3463f4 David Clift replied to the topic UCIS / UCDB in the forum OSVVM https://osvvm.org/forums/topic/ucis-ucdb#post-1638 Wed, 13 May 2020 12:30:19 +0100 Hi Michael,

Thank you all of FirstEDA are working from home so we have been very busy for the last few months supporting our customers.

No CoverageApiPkg.vhd is NOT for Modelsim/Questasim it is just the place holder for the function calls that are needed to interface to a simulators coverage database. As far as I am aware Aldec is the only…[Read more]

]]> 0 7013d10fdb872faecb9ea7834d35a8a0 David Clift replied to the topic UCIS / UCDB in the forum OSVVM https://osvvm.org/forums/topic/ucis-ucdb#post-1636 Wed, 13 May 2020 10:05:06 +0100 This is certainly possible, OSVVM contains an API package (VendorCovApiPkg.vhd) this is a set of foreign procedures that link OSVVM’s CoveragePkg coverage model creation and coverage capture with the built-in capability of a simulator.
Aldec have created a version of this (VendorCovApiPkg_Aldec.vhdVendorCovApiPkg_Aldec.vhd) to work with their…[Read more]

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