Thank you for your post. Whilst I agree that in general UVM is the number one verification framework for ASICS and FPGAs as seen in the 2020 Wilson research surveys. These statistics do not tell the full story as these results are across all industry segments. For DO-254 designs, we still see VHDL as the number one testbench language, even without the use of any advanced verification framework (UVM, OSVVM, etc). As Aldec we only have a couple of DO-245/CTS customers who are using UVM. I personally only know of one UK avionics company that used UVM, but this was for an ASIC, not an FPGA.
The certification authorities for DO-254 are conservative when it comes to design and verification tools, that’s why we have the structured tool qualification process. As such the certification authorities do accept UVM as a verification framework. The certification authorities may or may not expect some tool qualification or manual review data for the test self-checking capabilities. I don’t think they expect any tool qualification data for the entire verification framework.
So, as you say that UVM is generally accepted for DO-254, then the same reasoning can be used for OSVVM since both are advanced and well-structured verification frameworks. The certification authorities will expect the same level of tool qualification or manual review data for both UVM and OSVVM.
Application Specialist – FirstEDA Limited