Open Source VHDL Verification Methodology | fpgaphreak | Activity https://osvvm.org/members/engineer/activity Activity feed for fpgaphreak. Tue, 15 Sep 2026 01:22:50 +0100 https://buddypress.org/?v= en-US 30 hourly 2 ca9cb9dee8fa779beb7e2f258e6c9d27 fpgaphreak started the topic case splitting in the forum OSVVM https://osvvm.org/forums/topic/case-splitting Sun, 17 Mar 2024 01:55:11 +0000 In some cases i need a full coverage of cases when doing simulations of timing critial circuits which cause deviations in behaviour. I would like to know if OSVVM supports this in any way.

To understand the issue I would like to describe the problem:

Take a signal of unknown phase and level and a synchronizer to get it into a circuit with an…[Read more]

]]> 0 b1b26512d10509cea22886131f0b73d2 fpgaphreak replied to the topic Creating Asynchronous Clocks in the forum OSVVM https://osvvm.org/forums/topic/creating-asynchronous-clocks#post-2358 Sun, 17 Mar 2024 01:28:48 +0000 Me too. What is about Jitter Simulation with min/max definitions of the phase to simulate short term jitter effects?

]]> 0 46c3465318021ff1e7c594182474086d fpgaphreak replied to the topic I2C Bus pins simulation? in the forum VHDL https://osvvm.org/forums/topic/i2c-bus-pins-simulation#post-2357 Sun, 17 Mar 2024 01:21:59 +0000 Although old, a late response: This topic is often discussed together with pull ups constrained in the XDC for a pin which hardly can be simulated. Together with timing demands and driver issues, which are the common problems at I2C I recommend to use an analog behaviour model which transforms both the outout of the VHDL Pin and its input to a…[Read more]

]]> 0 86c6b8dcdf618fa6b709c303939e9ff9 fpgaphreak replied to the topic Xilinx not supporting VHDL anymore? in the forum VHDL https://osvvm.org/forums/topic/xilinx-not-supporting-vhdl-anymore#post-2356 Sun, 17 Mar 2024 01:16:16 +0000 I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.

Xilinx disreagards the fact that VHDL has certain…[Read more]

]]> 0 6e3b1f83d516d738b313d61b5c2f2d27 fpgaphreak replied to the topic Questa-Intel & Reports in the forum OSVVM https://osvvm.org/forums/topic/questa-intel-reports#post-2355 Sun, 17 Mar 2024 01:11:26 +0000 Questa Intel, yes.

]]> 0 c26821a41931e88cf5726b3cbe8dc442 fpgaphreak replied to the topic Custom VC for image-sensor interface in the forum OSVVM https://osvvm.org/forums/topic/custom-vc-for-image-sensor-interface#post-2123 Tue, 13 Dec 2022 20:15:15 +0000 So it seems more check for implementation issues rather than functional.(?)
I wonder how and in wich way one could alternatively simulation LVDS issues. Foussing on driever behavior?

]]> 0 fc778ee582ea0225ed0c3d155cbbee9f fpgaphreak replied to the topic Questasim Version in the forum OSVVM https://osvvm.org/forums/topic/questasim-version#post-2120 Sun, 11 Dec 2022 03:10:51 +0000 Was there any reaction of Siemens? I wonder who is working there at Questa anyway – i suggest these are the former Mentor programmers?

]]> 0 8347466653d0ef7f58d23d24a04686e6 fpgaphreak replied to the topic Questa-Intel & Reports in the forum OSVVM https://osvvm.org/forums/topic/questa-intel-reports#post-2119 Sun, 11 Dec 2022 03:05:51 +0000 I have the same issue here, but only newer Questa. Formerly i did not recognize this. Possibly a config issue.

]]> 0 52f55da1994a53649461f4217c3f6564 fpgaphreak replied to the topic Custom VC for image-sensor interface in the forum OSVVM https://osvvm.org/forums/topic/custom-vc-for-image-sensor-interface#post-2118 Sun, 11 Dec 2022 03:00:46 +0000 My question would be what the intention is in detail: Typically sensor interfaces are simulated and tested independently from the image content. Therefore I produced a test package capeable of driving various signal schemes and bahaviour into the lvds lines which can be simulated and also synthesized into an FPGA for real investigations of eye…[Read more]

]]> 0 8992e9c5a7d07d83886db5db0d68ccc7 fpgaphreak replied to the topic How to improve VHDL in the forum VHDL https://osvvm.org/forums/topic/how-to-improve-vhdl#post-2117 Sun, 11 Dec 2022 02:47:29 +0000 I still do not like the ambigious way, vectors are treated agains signals, and that there is conversion required in between a(0 downto 0) = “1” instead of using “a(0) = ‘1’). See the bram addressing regarding their write enable. This is one signal only, however one uses 0…0 instead of a signal. So VHDL could be made more tolerant for that.

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