I2C Bus pins simulation?

[Robert Freehart]

Does anyone have code that correctly simulates the SCL and SDA pins in VHDL?

I need to be able to simulate the functionality of those two pins for various masters and slaves.

[fpgaphreak]

Although old, a late response: This topic is often discussed together with pull ups constrained in the XDC for a pin which hardly can be simulated. Together with timing demands and driver issues, which are the common problems at I2C I recommend to use an analog behaviour model which transforms both the outout of the VHDL Pin and its input to a virtual voltage value which drives a virtual point in a circuit which is then driven by the wire too. Strength of pull up Rs and also driver issues can be most easily simulated.

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