Quick question. When trying to use memory package, I get an error when I try to initialize the memory with more than 31 bits as the data width. I can’t seem to find any information as to why this is the case or how to get around it.

In my test bench, the bus size is 32 bits and so I am trying to initialize the memory structure using a…[Read more]

I was wondering if there was a prebuilt OSVVM Scripting Function that does the following:

if “not included – OSVVM_Libraries” then
include ./OsvvmLibraries.pro
end if

I can use the TCL functions to do it, but I was wondering if there was already something there before I reinvent the wheel. This would significantly reduce the…[Read more]

Thanks for the info! I am planning on making one VC that encapsulates both tx and rx, but takes two transaction interfaces so that you can send and receive independently. Similar to how you mentioned in your first paragraph.

Due to how much the tx and rx need to talk to each other with regards to flow control and intialization, I am…[Read more]

I have a question about how one might go about creating a VC for a communication protocol such as SpaceWire, where there is no clear Master/Slave relationship between the nodes.

My concern is that in order to establish a connection with a SpaceWire node, some handshaking needs to be done between the sender and receiver. Due to the fact…[Read more]

One more quick question now that the expression and branch coverage report is working.

I see that Riviera has robust FSM code coverage reporting capabilities which I hope to be able to leverage in conjunction with OSVVM. I was wondering if the SetCoverageAnalyzeEnable function allows a user to gather FSM code coverage? Currently the…[Read more]

Thanks for the quick response. You’re suggestion worked and I am now only collecting the desired coverage information.

I am not running Riviera-PRO in batch mode, but I will be able to work with the current setup thanks to your reply.

Regards,
Michael

I am trying to incorporate Aldec’s code coverage with OSVVM and I seem to be running into an issue which I suspect is due to a scripting error on my part.

This is my current .pro file which I am using to compile and simulate my project, which I call using a .do file in Riviera:
(the .do file is where I source the startup.tcl and build the…[Read more]

One more quick question, my DUT also does the reverse… takes data from 21 UARTs and mux’s it all to one serial output. So while I haven’t gotten around to it yet, the next part of my test bench is going to have 21 UART_TX VC’s in it.

Would I be correct in assuming that I…[Read more]

I am simulating with Aldec Riviera Pro v.2019.10

Regards,
Michael

I have a DUT which takes in serial data, deframes it, and demux’s it out to a 21 peripheral UART’s for transmission.

I have written an OSVVM testbench for this, as an exercise in familiarizing myself with OSVVM, and I have ran into one issue. Everything else works amazingly.

In my test harness, instead of declaring 21 instances of a…[Read more]

I have a generic question regarding how one goes about interfacing with a DUT given a non-standard bus/interface.

Say for example I have an extremely simple DUT that uses a bus general reads and writes, lets call it DeviceBus, as well as two single bit wide PRBS_out and PRBS_in ports that are not a part of the DeviceBus…[Read more]