Code Coverage with Aldec Riviera Pro

[Michael]

Hello,

I am trying to incorporate Aldec’s code coverage with OSVVM and I seem to be running into an issue which I suspect is due to a scripting error on my part.

This is my current .pro file which I am using to compile and simulate my project, which I call using a .do file in Riviera:
(the .do file is where I source the startup.tcl and build the osvvmlibraries.pro)

# Test Suite for reporting purposes
TestSuite DMC_test_case_1

# Library to build
library work

##########################################################################
# Analyze hdl files
##########################################################################

analyze ./hdl/TMR/hdl/hdl_TMR/TMR.vhd

# DUT
SetCoverageAnalyzeEnable true
analyze ./hdl/Dynamic_Mux_Controller.vhd
SetCoverageAnalyzeEnable false

##########################################################################
# Analyze tb files
##########################################################################

# TMR
analyze ./tb/hdl/Prescale_Counter_TMR/hdl/hdl_TMR/TMR.vhd
analyze ./tb/hdl/Prescale_Counter_TMR/hdl/hdl_TMR/tmr_reg.vhd

# Usefuls
analyze ./tb/hdl/Prescale_Counter_TMR/hdl/hdl_Usefuls/Usefuls.vhd

# Prescale Counter
analyze ./tb/hdl/Prescale_Counter_TMR/hdl/hdl_Prescale_Counter_TMR/Prescale_Counter_TMR.vhd

# Test Bench
SetCoverageSimulateEnable true
analyze ./tb/packages/Dynamic_Mux_Controller_component_pkg.vhd
analyze ./tb/test_control/test_control_entity.vhd
analyze ./tb/Dynamic_Mux_Controller_tb.vhd

RunTest ./tb/test_control/test_case_1.vhd
SetCoverageSimulateEnable false

When I go to read the generated code_coverage.html that aldec produces, It reports minimal coverage because it seems to be analyzing all of the OSVVM packages for coverage as well as my DUT. I can see my DUT getting full coverage but the reporting is obscured by all of the packages that aren’t exercised in my design/test.

I’m wondering how to tell Aldec that I want to omit the OSVVM packages from code coverage. I know I can do it using the appropriate acdb arguments, but because I am using “Analyze” and “RunTest” I seem to be one layer of abstraction removed from Aldecs native commands. Any help would be greatly appreciated.

Regards,
Michael

[Jim Lewis]

Hi Michael,
First a quick answer:
Do “SetCoverageSimulateEnable true” before you build OSVVM libraries as well as anything else you don’t want coverage collected for.

Why:
Currently when analyze is run for Riviera-PRO by default we do:
vcom -${VhdlVersion} -dbg -relax -work ${LibraryName} {*}${OptionalCommands} ${FileName}

The “-dbg” flag is for debugging. Interestingly it also signals Riviera-PRO to collect certain coverage metrics.

When you do “SetCoverageSimulateEnable true” it runs the above vcom without the “-dbg” flag.

This is something that will be addressed in the next release (end of June). Especially as when OSVVM is analyzed, most do not need the “-dbg” flag set.

Are you running Riviera-PRO interactively or batch (such as using vsimsa console)? If you are using vsimsa console, I can I can do a quick fix (because we already detect this) – otherwise, some though has to be put into feature naming.

Best Regards,
Jim

[Michael]

Hey Jim,

Thanks for the quick response. You’re suggestion worked and I am now only collecting the desired coverage information.

I am not running Riviera-PRO in batch mode, but I will be able to work with the current setup thanks to your reply.

Regards,
Michael

[Michael]

Hey Jim,

One more quick question now that the expression and branch coverage report is working.

I see that Riviera has robust FSM code coverage reporting capabilities which I hope to be able to leverage in conjunction with OSVVM. I was wondering if the SetCoverageAnalyzeEnable function allows a user to gather FSM code coverage? Currently the .html that is being generated only has branch and expression coverage.

Do you know if that is currently supported within the OSVVM commands, or would that be something I would have to do directly through Riviera?

Regards,
Michael

[Jim Lewis]

Hi Michael,
The intention is that it reports statemachine options. Maybe I am missing something in the scripts?

You can set the specific options you want with SetCoverageAnalyzeOptions and SetCoverageSimulateOptions. The defaults for Riviera-PRO are as follows. I thought the “m” here is for statemachines.

SetCoverageAnalyzeOptions "-coverage sbm"
SetCoverageSimulateOptions "-acdb -acdb_cov sbm -cc_all"

The SetCoverageAnalyzeOptions results in calls to vcom of the following format:
vcom -2008 -relax -work DesignLib -coverage sbm Design1.vhd

The SetCoverageSimulateOptions results in calls to vsim of the following format:
vsim -acdb -acdb_cov sbm -cc_all -t ps -lib TestLib Test1

For merge OSVVM does:
acdb merge -o TestSuite.acdb -i Test1.acdb -i Test2.acdb -i Test3.acdb

For reporting OSVVM does:
acdb report -html -i TestSuite.acdb -o TestSuite.html

Am I missing a switch to cause the statemachine reports to be generated?

Regards,
Jim

[Jim Lewis]

Hi Michael,
I may have specified an extra attribute during simulation. You can adjust for this by doing:
SetCoverageSimulateOptions "-acdb_cov sbm -cc_all"

But it still did not report anything, so I read more into the the Aldec Riviera-PRO reference manual:
> Riviera-PRO does not automatically recognize the finite state machines from code. The user should embed the dedicated pragmas within code in order to obtain the coverage statistics.

So for the statemachine in UartRx.vhd from OsvvmLibraries/UART/src, I added the following attributes to the process

UartRxStateProc : process
  begin
    -- Aldec enum RxStateType CURRENT=RxState
    -- Aldec enum RxStateType STATES=RX_IDLE,RX_HUNT,RX_DATA,RX_PARITY,RX_STOP,RX_BREAK
    wait until Uart16XClk = '1' ;

That got this example working. Although, I am not sure it is so happy that I used the wait statement in my 1 process statemachine.

Best Regards,
Jim

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