Open Source VHDL Verification Methodology | Mikkie | Activity https://osvvm.org/members/mikkie/activity Activity feed for Mikkie. Sat, 18 Apr 2026 11:02:25 +0100 https://buddypress.org/?v= en-US 30 hourly 2 a0479a876693d665bafcb06b0acd1a7a Mikkie replied to the topic Handling expected failures in the forum OSVVM https://osvvm.org/forums/topic/handling-expected-failures#post-2777 Sat, 27 Sep 2025 15:00:01 +0100 Fantastic, thanks for the quick reponse.

]]> 0 1c86eb2f8801c0d5b834f353f8ea84c9 Mikkie started the topic Handling expected failures in the forum OSVVM https://osvvm.org/forums/topic/handling-expected-failures Sat, 27 Sep 2025 07:57:40 +0100 I have a test that create a single failure on a transition from one mode to the other. How can I tell OSVVM that this error is expected. The AffirmIF runs multiple times in the loops and in one loop iteration it fails. The iteration may be different depending on the timeout settings, so i cannot just check the iteration count. I would rather have…[Read more]

]]> 0 c92439d2e346402895078ce196a3635f Mikkie replied to the topic Combining Results from Multiple Runs into One HTML Report in the forum OSVVM https://osvvm.org/forums/topic/combining-results-from-multiple-runs-into-one-html-report#post-2774 Sat, 27 Sep 2025 07:53:08 +0100 Just chiming in on this topic, I was going to ask the same question re. combining multiple tests into a single report.
@David, can you give some pointer on how to combine the coverage from Questa?

]]> 0 443c1abd094ab3afc764da3ac0abdabf Mikkie replied to the topic OSVVM nad Siemens HDL Designer in the forum OSVVM https://osvvm.org/forums/topic/osvvm-nad-siemens-hdl-designer#post-2665 Mon, 31 Mar 2025 15:27:15 +0100 Hi Jim, you are right, probably there is a way. But, I won’t spend too much time on it for now.

If you want, I can try and work with you on the Avalon MM. I need it for a project.

]]> 0 569b3c868d5ef90a91996160f84ba890 Mikkie replied to the topic OSVVM nad Siemens HDL Designer in the forum OSVVM https://osvvm.org/forums/topic/osvvm-nad-siemens-hdl-designer#post-2663 Mon, 31 Mar 2025 08:21:25 +0100 On another note, on gitter I asked about progress/status of Avalon MM.

]]> 0 2fc5934cccc19ee805c7d9bb0d61e93c Mikkie replied to the topic OSVVM nad Siemens HDL Designer in the forum OSVVM https://osvvm.org/forums/topic/osvvm-nad-siemens-hdl-designer#post-2662 Mon, 31 Mar 2025 08:20:09 +0100 Hi Jim, Questa 2024.2.
My “issue” is not really with Questa. If I recall correctly I was able to do the demo tests when following the instruction in the documentation (by the way, great documentation) and running the scripts in Questa.

I was more asking about how to integrate it into the Siemens HDL Designer Pro flow. HDP provides a nice way to…[Read more]

]]> 0 a382d9fcc091714e8c0846d4a668a9ef Mikkie replied to the topic AHB, AHB-Lite, APB and AXI3 BFMs in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/ahb-ahb-lite-apb-and-axi3-bfms-in-osvvm#post-2660 Mon, 31 Mar 2025 02:50:52 +0100 Hi Jim, can you give a status update on the Avalon MM VC? I need it for a new project and don’t want to re-invent the wheel.

]]> 0 99f1d73fee23b9685e4d7a583d31f62d Mikkie started the topic OSVVM nad Siemens HDL Designer in the forum OSVVM https://osvvm.org/forums/topic/osvvm-nad-siemens-hdl-designer Mon, 31 Mar 2025 02:26:10 +0100 I would love to start using OSVVM. My current design flow is through Siemens HDL Designer. Is there a guide in setting up HDL Designer to make use of OSVVM?
I imported the OSVVM library into an HDL Designer mapped library, but get so many errors trying to simulate the DPRam example that I do not know where to start.
I am sure I am not the first…[Read more]

]]> 0 eea8bd3e61134f1e12f23180b2bc75fd Mikkie's profile was updated https://osvvm.org/activity/p/10663 Mon, 31 Mar 2025 02:22:04 +0100 0 dcb4b0a3272dc6e5d586b405848d916f Mikkie became a registered member https://osvvm.org/activity/p/10540 Thu, 30 Jan 2025 11:46:46 +0000 0