OSVVM nad Siemens HDL Designer

[Mikkie]

I would love to start using OSVVM. My current design flow is through Siemens HDL Designer. Is there a guide in setting up HDL Designer to make use of OSVVM?
I imported the OSVVM library into an HDL Designer mapped library, but get so many errors trying to simulate the DPRam example that I do not know where to start.
I am sure I am not the first to try this, hence asking for help here.

Thanks in advance

[Jim Lewis]

Hi Mikkie
What version of Questa are you using?

With 2024.2 I turned on VHDL-2019. The features work fine, but in 2025.1 Questa decided to throw warnings for this feature.

If it is not 2025.1, then it is probably too old like 10.4 or 10.5.

I have been running regressions with 2024.3_1.

Best Regards
Jim

[Mikkie]

Hi Jim, Questa 2024.2.
My “issue” is not really with Questa. If I recall correctly I was able to do the demo tests when following the instruction in the documentation (by the way, great documentation) and running the scripts in Questa.

I was more asking about how to integrate it into the Siemens HDL Designer Pro flow. HDP provides a nice way to perform the lego block connecting of blocks and also generates the documentation, so I would like to continue with this flow, however, it is not the end of the world if it is not supported, I can use text editor..
I was hoping to start migrating my existing HDP testbenches to osvvm by adding new architectures to the old testers.

[Mikkie]

On another note, on gitter I asked about progress/status of Avalon MM.

[Jim Lewis]

I have not seen Siemens HDL Designer Pro flow, so I cannot comment on how to use it. Like most things there may be a way.

Avalon MM is progressing slowly.

[Mikkie]

Hi Jim, you are right, probably there is a way. But, I won’t spend too much time on it for now.

If you want, I can try and work with you on the Avalon MM. I need it for a project.

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