I must have missed this when initially going through the github docs but this configuration based implementation is what I was looking for so very much appreciated!

I will look into doing this today to do some hands on testing but am I reading this right in that this multiple test suite configuration would allow for…[Read more]

I’m looking to increase sim times for some longer running test suites and was looking at using the open source VUnit model with Riviera-PRO to accomplish this. I know the VUnit is separate from OSVVM but since you’ve done some work with them you may be able to point be in the right direction.

First, I don’t believe OSVVM offers support…[Read more]

Was able to alias the buried signal and then use force in to drive it from the testcase giving me more control over the specific time that the signal changed during testing.

Thanks Jim.

So I’m not seeing anything that would lead me to believe forcing signals to a defined value is possible via OSVVM but wanted to put it out there incase I’m missing some obvious switch or something.

When pushing to fully verify our code we often get to the point that only error states are not being exercised. I would like to force a signal…[Read more]

This is awesome news, I really appreciate the continued updates to these libraries.

Regarding clock jitter, looking into the code in ClockRstPkg.vhd I’m not sure I fully understand what is happening with the supplied coverage ID. Has there been a documentation update which details this new function?

I would expect a jitter clock to…[Read more]

The error message was referencing an all uppercase $ALDEC but “global aldec” fixed this issue. I noticed the same thing with “puts $aldec” vs “puts $ALDEC” as you describe.

No, there is no $aldec used in the $PATH_TO_SIM_DIR on my machine, that just points to the project directory on my C:/ drive.

Thanks,
Brad

I totally agree. This is part of what was so confusing to me. I could see that when using $aldec and running the test the variable would be properly expanded as you show, however, a bit further into the run, when attempting to load the aldec_matlab_cosim.dll the path would still show an unexpanded variable $ALDEC in the path.

I actually…[Read more]

So I’ve been working with Aldec as well on this and we’ve tracked down the root cause of OSVVMs failure to correctly call the $ALDEC variable.

Turns out that we needed to add “global aldec” to the VendorScripts_RivieraPro.tcl within the vendor_simulate process.

I don’t think there is a way to add images on these forms to show you…[Read more]

At this point the remaining failure when using RunTest seems to be in the load libraries steps, specifically the libraries from Aldec. In the below console output, systf.dll and…[Read more]

Currently, I know the following script will allow my to run my test and see the results:

SetCoverageSimulateEnable true

analyze…[Read more]

So I’ve run into a bit of an issue with the usual OSVVM scripted flow and a testbench which aims to use some MATLAB cosim features. In short, I can successfully cosim if I don’t use RunTest or any of the TestName/analyze/simulate flow. In my experience the code coverage enabled via SetCoverageAnalyzeEnable/Set CoverageSimulateEnable only…[Read more]

Looking at TestStandAlone.vhd assume there is a generate statement that decides if xMiiPhy gets created or not.


phy_gen : if C_PHY_GEN_TRUE = 1 generate

xMiiPhy_1 : xMiiPhy
generic map (
MII_INTERFACE =>…[Read more]

glbl is a verilog file referenced by an IP from a third party vendor.

Is it possible to set a generic for a file that is analyzed before simulation? Looking at the script users guide I would think that SetExtendedAnalyzeOptions is meant to accomplish this but I could be using the command incorrectly. Is it possible to use…[Read more]

I’m wondering if there has been any documentation made for using some script functions with a dual-language testbench. Looking through past articles I’ve found discussion of topics that come close to what I am trying to do but none of which speak to .pro (or since I’m simulating in Riviera .do) considerations.

The core of what I am…[Read more]

As in the comment above if I do the following:

write(trans_rec, x”0001?, x”DEADBEEF”); –WSTRB = 1110

The AXIBUS data line shows t…[Read more]

So this is an atypical use case for sure.

Usually I use the Axi4Lite VC as ‘normal’ and if, for instance, I was sending 32-bit data to some addresses I would do:
write(trans_rec, x”0000″, x”DEADBEEF”);
write(trans_rec, x”0004″, x”DEADBEEF”);
write(trans_rec, x”0008″, x”DEADBEEF”);
Where the base address is increasing…[Read more]

So I guess my question becomes, is this still accurate and if so, is there a known way to work around this in OSVVM?

I’m using the AXI Lite manager VC to interface with a DUT which will eventually take what is written via AXI Lite and write it to a dpRAM.

The issue I’ve run into is that I see no way to properly decouple the data width from the strb width for this record. In this case my data width is 32-bits which means that the manager code…[Read more]

I’m not seeing any options for this within the CreateClock procedure, is there possibly another function that allows this behavior?

Thanks.

I misunderstood the correct way to use RECEIVE_READY_BEFORE_VALID and RECEIVE_READY_DELAY_CYCLES but this makes a lot of sense.

I’ve been using OSVVM for several months with great success but I’ve run into a problem with simulating backpressure. At a high level my test bench looks like the following:

AXIS Transmitter –> DUT –> AXIS Receiver

I’d like to test my DUT for operation in the case that the AXIS Receiver is not ready for more data but the transmitter…[Read more]