Support for Forcing DUT Signals via OSVVM

[Brad Adam]

Hey,

So I’m not seeing anything that would lead me to believe forcing signals to a defined value is possible via OSVVM but wanted to put it out there incase I’m missing some obvious switch or something.

When pushing to fully verify our code we often get to the point that only error states are not being exercised. I would like to force a signal to a value that would trigger the error handling logic via my testcase. I’m simulating using Riviera-PRO which does have support for ‘forcing’ a signal but this is limited and a bit clunky to trigger at the right time?

The signals I am trying to access would be buried deeper into the DUT with no direct connection to the top level. Ideally I could access them via the hierarchy path similar to the way an alias of the signal would be created:

alias sig_alias is <<signal .DUT_TB.u1.siganl_name : std_logic>>;

Does OSVVM provide some way of accessing signals in the DUT hierarchy and overriding them with another value? Or perhaps there is some simulate option that can take the force command in and use it during the simulation.

Appreciate any insight to this!

[Jim Lewis]

If the signals you want to drive are on an interface, then your verification component can be built so that it triggers all error conditions.

If the signals you want to drive are deep in your design, you can test that capability at the level where those signals are exposed.

Alternately if signals you want are deep in the design and you want to run the test at a testbench level where those signals are buried, then you need to drive the signals using the VHDL-2008 capability for external names. This is a VHDL thing and not an OSVVM thing.

Read up on using the VHDL-2008 force capability. To successfully use the VHDL-2008 force and external name capability, I would not be surprised if your simulator required both the testbench and design be compiled using VHDL-2008.

[Brad Adam]

I was not familiar with that VHDL-2008 capability but this did solve it for me!

Was able to alias the buried signal and then use force in to drive it from the testcase giving me more control over the specific time that the signal changed during testing.

Thanks Jim.

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