Open Source VHDL Verification Methodology | Hassan | Activity https://osvvm.org/members/curiousengineer/activity Activity feed for Hassan. Tue, 25 Aug 2026 14:27:19 +0100 https://buddypress.org/?v= en-US 30 hourly 2 622a8cc09ae52cf60dabb820c6fe310a Hassan started the topic OSVVM: Build part of design and run only single test in the forum OSVVM https://osvvm.org/forums/topic/osvvm-build-part-of-design-and-run-only-single-test Sat, 18 Oct 2025 21:05:08 +0100 Here are the steps:

First compile everything.
build ../OsvvmLibraries/OsvvmLibraries.pro
…

Later just compile the DUT, lets say that it is the AXI4.
build ../OsvvmLibraries/Axi4/Axi4/build.pro

Now compile the testbench for this DUT:
build ../OsvvmLibraries/Axi4/Axi4/testbench/build.pro

Now run single test:
RunTest…[Read more]

]]> 0 d8dbedb932ba3e65e7cf0d0f80672bb4 Hassan replied to the topic Parallel Simulations in OSVVM and VUnit Integration in the forum OSVVM https://osvvm.org/forums/topic/parallel-simulations-in-osvvm-and-vunit-integration#post-2782 Sun, 05 Oct 2025 22:29:34 +0100 Is there any update on this i.e can we now generate the reports of OSVVM from VUnit test framework based testbench?

]]> 0 3b57694e59c0a8e284585f84f9e7102f Hassan replied to the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL https://osvvm.org/forums/topic/why-does-vhdl-require-explicit-conversion-from-signed-unsigned-to-logic-vector#post-2550 Tue, 30 Jul 2024 11:57:27 +0100 In the VHDL as it exists today, we must use numeric_std. No arithmetic is thus possible with std_logic_vector, we must use signed or unsigned.

I do not understand, what logic or arithmetic principle is broken when signed is converted to std_logic_vector implicitly or unsigned is converted to std_logic_vector implicitly.

I am merely talking about…[Read more]

]]> 0 fbb890a72952ff749449221bf18685a8 Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL https://osvvm.org/forums/topic/convert-std_logic_vector-to-record#post-2549 Tue, 30 Jul 2024 11:52:24 +0100 I am just wondering how come the big names like Siemes, Mentor Graphics e.t.c don’t fund this group. Also, the government does not seem to show any keen interest to fund this. The evolution of technology requires tools to be in place. If the industry giants don’t come together to make it happen, who else is going to make it happen?

]]> 0 ef5d1dc6122370666052d863b4b8fc04 Hassan started the topic VHDL port map between std_logic_vector(0 downto 0) and std_logic in the forum VHDL https://osvvm.org/forums/topic/vhdl-port-map-between-std_logic_vector0-downto-0-and-std_logic Thu, 25 Jul 2024 21:52:34 +0100 When using generics to control data width of ports we could end up with std_logic_vector(0 downto 0) due to the data width being 1. When connecting this to an std_logic signal there is always an error of mismatch since there is std_logic_vector(0 downto 0) on on side and std_logic on the other side.

The way to deal with this issue is to do this…[Read more]

]]> 0 370bb7ab449b0c97f53313c39ca421c5 Hassan replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL https://osvvm.org/forums/topic/does-vhdl-contain-functions-like-verilog-readmemb-and-readmemh#post-2543 Thu, 25 Jul 2024 21:47:53 +0100 Thanks.

My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.

]]> 0 53157502c018f30a36fd0519beac9d44 Hassan started the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL https://osvvm.org/forums/topic/does-vhdl-contain-functions-like-verilog-readmemb-and-readmemh Thu, 25 Jul 2024 10:14:07 +0100 Verilog/SystemVerilog (synthesis) has some functions that can read a file into a signal. These are $readmemb and $readmemh. These can both be used to easily create a ROM from file contents. As far as I know, VHDL does not contain anything along these lines that will work in synthesis. Is this true? If so, why is this so?

]]> 0 eb78749a4caae3e618e2991ebbfba8c2 Hassan started the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL https://osvvm.org/forums/topic/why-does-vhdl-require-explicit-conversion-from-signed-unsigned-to-logic-vector Thu, 25 Jul 2024 00:00:18 +0100 The signed, unsigned and std_logic_vector are all ultimately based on the std_logic. Why does VHDL require explicit conversion from signed to std_logic_vector and unsigned to std_logic_vector?

]]> 0 190c7b5db2a4738e149eda40f570c0f5 Hassan replied to the topic The #if in VHDL in the forum VHDL https://osvvm.org/forums/topic/the-if-in-vhdl#post-2538 Wed, 24 Jul 2024 12:33:49 +0100 If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:

#if FEATURE1

#endif

#if FEATURE2

#if FEATURE3VER > 2

#else

#endif

#endif

How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be…[Read more]

]]> 0 4e0ec07fdff600481f5bd39bc1e0c187 Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL https://osvvm.org/forums/topic/convert-std_logic_vector-to-record#post-2537 Wed, 24 Jul 2024 12:30:22 +0100 One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than…[Read more]

]]> 0 f661525007d2ae5c91806b9a2e4b7c19 Hassan started the topic Convert std_logic_vector to record in the forum VHDL https://osvvm.org/forums/topic/convert-std_logic_vector-to-record Fri, 19 Jul 2024 19:35:20 +0100 Lets take an example,

constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;

type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;

Now…[Read more]

]]> 0 828dd46688124afa9cf3960474520b78 Hassan started the topic Mixed language simulation and synthesis support in the forum VHDL https://osvvm.org/forums/topic/mixed-language-simulation-and-synthesis-support Mon, 15 Jul 2024 13:14:50 +0100 One way in which hardware engineers are suffering is that there exist more than one RTL language and both of these can be used for writing testbenches although SystemVerilog has gone ahead since it was created from Verilog by integrating Hardware Verification Language features.

A serious issue that exists is that there is no set standard (from…[Read more]

]]> 0 b42776bbdb79ba7db8a881a80e3ebd0d Hassan replied to the topic The #if in VHDL in the forum VHDL https://osvvm.org/forums/topic/the-if-in-vhdl#post-2528 Sun, 14 Jul 2024 17:25:03 +0100 Doesn’t that feature only work with these things:

`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;

How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.

I mean using #if we…[Read more]

]]> 0 bd415f51a19de6d1b77799ba3ca80411 Hassan started the topic The #if in VHDL in the forum VHDL https://osvvm.org/forums/topic/the-if-in-vhdl Fri, 12 Jul 2024 12:18:35 +0100 I worked at an organization that designed very large digital designs, so large that no FPGA can fit them, millions and millions of gates. These designs had a lot of features that could be enabled or disabled using something they called configurations. A configuration would add or remove or change ports of interfaces. These would also affect other…[Read more]

]]> 0 d24d31fe307ee1f038b7cbd48039bc1b Hassan started the topic Bug in AxiStream Receiver for SetAxiStreamOptions that changes WaitForGet in the forum OSVVM https://osvvm.org/forums/topic/bug-in-axistream-receiver-for-setaxistreamoptions-that-changes-waitforget Sun, 30 Jun 2024 20:40:05 +0100 I require that when the simulation starts the AxiReceiver TReady is low and it stays this way until the VC is given command to read input. This is one of the tests that I have written.

The WaitForGet is declared in line 153 of the AxiStreamReceiver. I tried to change its state using SetAxiStreamOptions(StreamRxRec, RECEIVE_READY_WAIT_FOR_GET,…[Read more]

]]> 0 13d128146ec9e0cd714f718df4f9e09a Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM https://osvvm.org/forums/topic/optional-ports-on-axi-stream-transmitter-and-receiver-cannot-be-left-unused#post-2511 Sun, 23 Jun 2024 01:32:14 +0100 I believe that the GetAxiStreamOptions could just be used with DEFAULT_ID, DEFAULT_DEST, DEFAULT_USER. However, I am not sure why this is not done anywhere in any testbench that comes with OSVVM.

]]> 0 926d955b75dde3b8ee2261a0921d80bb Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM https://osvvm.org/forums/topic/optional-ports-on-axi-stream-transmitter-and-receiver-cannot-be-left-unused#post-2510 Sun, 23 Jun 2024 01:10:07 +0100 4. The AXI stream receiver gets the ID, DEST and USER from the transmitter VC. When it gets the data, we can access what the transmitter sent it. What then is the meaning of SetAxiStreamOptions for the receiver? It should only have GetAxiStreamOptions just like it has Get and no Send command. It is a receiver after all.

]]> 0 ca9f9080a94a54ffc7c0897c332386aa Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM https://osvvm.org/forums/topic/optional-ports-on-axi-stream-transmitter-and-receiver-cannot-be-left-unused#post-2509 Sun, 23 Jun 2024 01:02:29 +0100 The USER can be assigned as follows:
SetAxiStreamOptions(StreamTxRec, DEFAULT_USER, User);

Or, within the send and sendburst commands:
Send(StreamTxRec, X”AAAA_AAAA”, ID1 & DEST1 & USER1 & ‘0’, TRUE) ;
SendBurst(StreamTxRec, 8, ID2 & DEST2 & USER2 & ‘1’) ;

The check can be done like this:
Check(StreamRxRec, X”BBBB_BBBB”, ID1 & DEST1 & USER1 &…[Read more]

]]> 0 f6245998e51f84e9a2c1b3d835415385 Hassan replied to the topic Dissecting usage of DelayCoveragePkg in the forum OSVVM https://osvvm.org/forums/topic/dissecting-usage-of-delaycoveragepkg#post-2507 Sat, 22 Jun 2024 18:00:27 +0100 What is the meaning of writing something like this: GenBin(2,10,2) where the number of bins is more than one, as far as the DelayCoverage Model is concerned?

]]> 0 2e7b9e019d5208d2ae32f1c078137b2c Hassan started the topic Dissecting usage of DelayCoveragePkg in the forum OSVVM https://osvvm.org/forums/topic/dissecting-usage-of-delaycoveragepkg Sat, 22 Jun 2024 16:20:51 +0100 When I started reading the OSVVM documentation, I left the DelayCoveragePkg and the CoveragePkg for last. I had assumed that both of these are related to functional coverage which is more relevant when pseudo-random stimulus based testbench is used. It was only later that I realized that the DelayCoveragePkg serves a completely different purpose…[Read more]

]]> 0 558bf9ac0892948a2acb4aed0ede4ee8 Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM https://osvvm.org/forums/topic/optional-ports-on-axi-stream-transmitter-and-receiver-cannot-be-left-unused#post-2503 Tue, 18 Jun 2024 21:52:56 +0100 I guess converting it into record is the correct way forward in that case, since that is how it works with the memory mapped AXI4 VC.

So is there any example that uses the AxiStreamGenericSignalsPkg at the moment?

]]> 0 e3dde172a198b1753ff791ccbc58130c Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM https://osvvm.org/forums/topic/optional-ports-on-axi-stream-transmitter-and-receiver-cannot-be-left-unused#post-2501 Tue, 18 Jun 2024 00:43:04 +0100 One more thing. I created the dummy signals but the forgot to update this line:

constant AXI_PARAM_WIDTH : integer := TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH + 1 ;

I had to add the TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH back into them. Certainly the setup feels rather fidly.

]]> 0 137afa6a8e3c6d124c8d6aaaf6d97402 Hassan started the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM https://osvvm.org/forums/topic/optional-ports-on-axi-stream-transmitter-and-receiver-cannot-be-left-unused Mon, 17 Jun 2024 23:29:27 +0100 I have used the AXI stream testbench to create my own for my design. The thing is, I do not need to use all the optional signals that are part of the AXI Stream interface. I am only using these on my DUT: valid, enable, data, user. I am not using these on my DUT: TID, TDest, TUser, TStrb, TKeep, TLast.

For the unused AXI stream signals on my DUT…[Read more]

]]> 0 47b5140bd0aebf99ce4b767b7c34985d Hassan replied to the topic VHDL Assert that prints the entity instance name and path in the forum VHDL https://osvvm.org/forums/topic/vhdl-assert-that-prints-the-entity-instance-name-and-path#post-2498 Sun, 16 Jun 2024 13:57:41 +0100 I have used these 3 attributes in a process but it seems that Quartus synthesis does not support any of them at all. It just gives error “predefined attribute … is not supported”

p_assert_generics: process
begin

report p_assert_generics’simple_name severity warning;
report p_assert_generics’instance_name severity warning;…[Read more]

]]> 0 44931669110a46125e033be8b39b768e Hassan started the topic VHDL Assert that prints the entity instance name and path in the forum VHDL https://osvvm.org/forums/topic/vhdl-assert-that-prints-the-entity-instance-name-and-path Sun, 16 Jun 2024 11:21:02 +0100 This question is specifically about Assert used to validate the generics of VHDL entity. It is clear that one can use Assert statement to check the value of generic and if the assert fails, the synthesis will stop with error.

There are two basic questions about this:

1. Should such an Assert statement be inside or outside process? Different…[Read more]

]]> 0 3a7e3b99f171ab88b8f2328f9dccbe5a Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm#post-2480 Fri, 07 Jun 2024 00:56:15 +0100 I can see that the scripts use the explicit name of the file for analyze and run_test TCL commands. However, it is also possible to just do a file search and with the filenames in a list, iterate over the list and call analyze or run_test for each of them.

Why isn’t it done in this way?

Also, I was expecting to see a whole lot of commands that…[Read more]

]]> 0 8297b01e4498c88f0ae2aef4f51685af Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository/page/2#post-2479 Thu, 06 Jun 2024 23:08:21 +0100 When OSVVM is compiling files, I get a whole lot of messages like this:

# QuestaSim-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 23:57:14 on Jun 06,2024
# vcom -2008 -work osvvm_cosim ../OsvvmLibraries/CoSim/src/CoSimInterruptHandler.vhd
# — Loading package STANDARD
# — Loading package TEXTIO
# — Loading package std_logic_1164
# –…[Read more]

]]> 0 2c798d045aa75825d527dce8b18b254a Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm#post-2463 Wed, 05 Jun 2024 15:20:42 +0100 The functions that are used to perform interface transactions and directive transactions are quite flexible and numerous. They include blocking and non-blocking calls aka asynchronous. These applies to the manager and subordinate, both read and write and also check functions.

Why is there need to have both blocking and non-blocking function…[Read more]

]]> 0 a763f8c07a6e446180020d4c415db947 Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm#post-2462 Wed, 05 Jun 2024 15:13:10 +0100 The MIT document for streaming and address mapped interfaces states this: “One of the challenges of using a single record, such as AddressBusRecType, as an interface is dealing with multiple drivers on each record element. OSVVM does this giving each element a resolved type, such as bit_max, std_logic_vector_max_c, integer_max, time_max, and…[Read more]

]]> 0 9492b7eea6b95ec0f4b8eee0d5c713ae Hassan replied to the topic Check functions in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/check-functions-in-osvvm#post-2459 Tue, 04 Jun 2024 09:37:30 +0100 The scoreboards can contain tags for “out of order” transactions and can also drop transactions. This makes them more sophisticated then mere FIFOs. But what more features could they be given when you say “There is a long term plan to give users more direct control of the output of scoreboards.”

]]> 0 c247125b5cec589e659710aca500918c Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm#post-2456 Mon, 03 Jun 2024 00:28:12 +0100 This code confused me and is found in the AXI4 manager source:

— Initialize DelayCoverage Models
AddBins (WriteAddressDelayCov.BurstLengthCov, GenBin(2,10,1)) ;
AddBins (WriteAddressDelayCov.BeatDelayCov, GenBin(0)) ;
AddBins (WriteAddressDelayCov.BurstDelayCov, GenBin(2,5,1)) ;

…

— Valid Delay between…[Read more]

]]> 0 8b5153e8248ddb3682d72e70032b5eac Hassan replied to the topic Log, Alert and Affirm in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/log-alert-and-affirm-in-osvvm#post-2455 Sun, 02 Jun 2024 21:57:00 +0100 That means normally we would not need to use Alert, but only the Affirm functions?

By the way, I did attend your course on OSVVM many years ago, before COVID. I was quite unwell in that week when I attended and could not absord the finer points. I had one more colleague with me. That colleague left a few wekks later and a redundancy drive a few…[Read more]

]]> 0 bf7c857c7c03fefec4e63a7866ccb03e Hassan started the topic Check functions in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/check-functions-in-osvvm Sun, 02 Jun 2024 18:11:25 +0100 When looking at the VC documentation and related code, I came across Check functions of OSVVM. Here are a few examples:

E:My_DesignsFPGAOsvvmLibrariesCommonsrcAddressBusTransactionArrayPkg.vhd (14 hits)
Line 303: procedure ReadCheck (
Line 504: procedure ReadCheckBurstVector (
Line 514: procedure ReadCheckBurstIncrement (
Line…[Read more]

]]> 0 e463c62f242a1b0a66a06f1b072ce649 Hassan started the topic Log, Alert and Affirm in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/log-alert-and-affirm-in-osvvm Sun, 02 Jun 2024 00:50:50 +0100 The AlertLogPkg contains three type of functions:

Log; this has following levels: ALWAYS, DEBUG, FINAL, INFO, PASSED

Alert; this has following variants: Alert, AlertIf, AlertIfNot, AlertIfEqual, AlertIfNotEqual, AlertIfDiff. THe alert has following levels: FAILURE, ERROR, WARNING.

Affirm; this has following variants: AffirmIf, AffirmIfNot,…[Read more]

]]> 0 db212f63e26917a84779c7aaed977f10 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository/page/2#post-2448 Sun, 02 Jun 2024 00:29:36 +0100 I understand that all of these are basically FIFOs. The term “scoreboard” need not confuse oneself.

]]> 0 8d807c2b327d10683a73612a22bde59f Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm#post-2447 Sun, 02 Jun 2024 00:25:37 +0100 The AXI4Manager source code contains these lines in the architecture declaration part:

signal WriteAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal WriteDataFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;

signal ReadAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal…[Read more]

]]> 0 7a26f14e343a85c221d6f3b5f1b418a4 Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm#post-2446 Sun, 02 Jun 2024 00:20:09 +0100 It seems that so many IDs are needed to create a hierarchical output for difference aspects of the BFM in the test result report.

]]> 0 324c88106cdddd7ebe48ed7909adcad7 Hassan replied to the topic How to improve VHDL in the forum VHDL https://osvvm.org/forums/topic/how-to-improve-vhdl#post-2441 Fri, 31 May 2024 21:31:59 +0100 What is the primary benefit of this thread since the synthesis tool vendors will take maybe a decador or more to add simple new features for the language.

We need an effort to upgrade the flow that is used with VHDL. We need something like LLVM for VHDL. The netlist fitter can be handled by the tools. But tool for synthesis and compilation for…[Read more]

]]> 0 4f415b68efb64372467f464417295ed6 Hassan started the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM https://osvvm.org/forums/topic/dissecting-the-osvvm-axi-master-bfm Fri, 31 May 2024 21:21:48 +0100 This thread has been created to ask questions about the Axi4Manager found in the OSVVM AXI4 portion. This is the full AXI4 Master BFM. There is a separate BFM for the AXI4-Lite. There are two primary variants of the Axi4Manager. These are one variant without VTI (Axi4Manager) and one with VTI (Axi4ManagerVti). These only differ in how the…[Read more]

]]> 0 152ecb86319e745b138833be4ec6d121 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository/page/2#post-2437 Fri, 31 May 2024 11:33:37 +0100 The AXI4Manager source code contains these lines in the architecture declaration part:

signal WriteAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal WriteDataFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;

signal ReadAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal…[Read more]

]]> 0 fd543e7bf16c7a02a9d819010397faba Hassan replied to the topic Can OSVVM Verification Component be used in VUnit based testbench? in the forum OSVVM https://osvvm.org/forums/topic/can-osvvm-verification-component-be-used-in-vunit-based-testbench#post-2426 Wed, 22 May 2024 21:57:28 +0100 OSVVM can generate a lot of test reports at end of a test, I believe the EndOfTestReports exists for this purpose.

Is this feature compatible with VUnit or does it require specific OSVVM scripts and script commands to be run before those design reports can be created?

]]> 0 b295e23e4d02ab162fe961722db05e25 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository/page/2#post-2422 Tue, 21 May 2024 19:52:46 +0100 The TbAXI4.vhd contains AXI4 Manager and Subordinate along with the Test controller/sequencer called TestCtrl. It also contains clock and reset source.

There is one more thing called Axi4Monitor. I found a source file called Axi4Monitor_dummy.vhd which has an entity but empty architecture. Does this mean that the monitor module is not yet…[Read more]

]]> 0 3435d830ec67c5adc7b0a6197ab28cf3 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository#post-2420 Fri, 17 May 2024 21:16:32 +0100 I was suspecting that the only method will be to use a wrapper that only uses standard logic signals and then the Platform Designer and Block Designer should not have any issue. Its amazing how poor the hardware domain EDA tools are.

]]> 0 50392b15e8c827af1608c384d0345117 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository#post-2418 Fri, 17 May 2024 00:08:24 +0100 Thanks Jim. Now for a simpler question.

Often the BFM is going to used with a System created using Platform Designer in Quartus or the System Builder in Vivado.

For Platform Designer this means that we create a tcl file that tells the tool what signals make up the AXI interface so it can link them with the complementing master/slave port and…[Read more]

]]> 0 c819920a0070c9e4d9204cdbeed614d9 Hassan replied to the topic AHB, AHB-Lite, APB and AXI3 BFMs in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/ahb-ahb-lite-apb-and-axi3-bfms-in-osvvm#post-2417 Thu, 16 May 2024 16:19:50 +0100 I did need these in the past at one point but I eventually used a bridge component than converted the AHB-Lite and APB transaction into basic MM transaction just with minimum signals on the other side and I finished the work using them. Throughput did not matter much in that specific scenario since it was reading or writing some few hundreds of…[Read more]

]]> 0 928bbb520adac38b11e7a8662bd7a3e3 Hassan started the topic AHB, AHB-Lite, APB and AXI3 BFMs in OSVVM in the forum OSVVM https://osvvm.org/forums/topic/ahb-ahb-lite-apb-and-axi3-bfms-in-osvvm Wed, 15 May 2024 23:40:05 +0100 AMBA contains many buses, some of which are old but still used possibly for simpler low bandwidth applications. These include things like AHB, AHB-Lite and APB. It also includes AXI3. Is there any plan to create BFMs for these as well?

I am only trying to understand the level of effort being spent to create BFMs for popular data buses for the…[Read more]

]]> 0 2a063c76481bb9314f3e74fb0d3ae930 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository#post-2412 Wed, 15 May 2024 23:28:38 +0100 OK, so here is how I am able to run specific test.

First I goto a suitable location where QuestaSim can save its generated files. In this case I did

cd {E:My_DesignsFPGAOsvvmLibraries}

Then I ran the following commands:

source ./Scripts/StartUp.tcl
include ./osvvm/osvvm.pro
include ./Common/Common.pro
include ./AXI4/AXI4.pro

library…[Read more]

]]> 0 41859534766db9638bdb6ac8f1968ab0 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository#post-2411 Wed, 15 May 2024 22:48:05 +0100 First lets look at RunDemoTests.pro

TestSuite Axi4Full
library osvvm_TbAxi4

if {$::osvvm::ToolNameVersion ne “XSIM-2023.2”} {
include ./testbench

# Make TestCases the frame of reference
set ::osvvm::CurrentWorkingDirectory [file join $::osvvm::CurrentWorkingDirectory TestCases]
RunTest TbAxi4_DemoMemoryReadWrite1.vhd
RunTest…[Read more]

]]> 0 2ad9f8bc540e36ecaf456bd03d8f0660 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository#post-2410 Wed, 15 May 2024 19:25:28 +0100 Jim I agree with you that once a test passes, it will never ever be run interactively and only in regression. I agree that the only time a test is run interactively is when a test is being developed or it fails and a closer look at waves is required.

The simple answer to the question is that to know what tests exist, we look at the test plan or…[Read more]

]]> 0 131d7a3c1f3db309c490058ab7e65784 Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM https://osvvm.org/forums/topic/running-axi4-simulation-from-osvvm-repository#post-2406 Wed, 15 May 2024 11:19:19 +0100 Thanks Jim. I know you are busy but still taking time out to write here.

With VUnit I can pass a switch to the run.py and get list of tests and then run a specific test. I can choose whether to run it in in GUI mode or batch mode. How can I do that with OSVVM AXI4 tests?

I can see that with OSVVM, each test is a different architecture of the…[Read more]

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