One way in which hardware engineers are suffering is that there exist more than one RTL language and both of these can be used for writing testbenches although SystemVerilog has gone ahead since it was created from Verilog by integrating Hardware Verification Language features.
A serious issue that exists is that there is no set standard (from what I know) that defines how the two languages must integrate e.g instantiate VHDL entity in SV module or vice versa or calling functions in SV package from VHDL.
What is the reason that the higher powers that define the evolution of the language never bothered to sit down and define how the two languages can be made compatible so they can simulate and synthesize harmoniously e.g VHDL supporting SV interfaces e.t.c. When a definition exists for mixed language simulators and synthesis tools, the vendor will have to eventually support it and over the next 25 years, our life will become gradually easier.
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