Lets take an example,
constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;
type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;
Now converting MyRecord to slv is quite simple. We just need to be sure that we do it the same way everywhere or better write a function. If the value of field length changes, there is no problem here:
slv := field1 & field2 & field3;
Now converting from slv to MyRecord is not straightforward since it needs many lines of code.
— Function to convert std_logic_vector to MyRecord
function to_MyRecord(slv : std_logic_vector(11 downto 0)) return MyRecord is
variable rec : MyRecord;
begin
rec.field1 := slv(field3_len+field2_len);
rec.field2 := slv(field3_len+field2_len-1 downto field3_len);
rec.field3 := slv(field3_len-1 downto 0);
return rec;
end function;
Now writing these functions takes time and is tedious. If the record changes we need to update all the functions. The biggest problem is that if we have records with a large number of fields and a new field is added in the middle (just we need to do that sometimes for reasons outside of control), then it is quite easy to make mistake in the modifying of slv to record function.
SystemVerilog does not need this type of conversion. My question is, why doesn’t VHDL provide a built in method to convert from slv to record?
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