Convert std_logic_vector to record
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Hassan.
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July 19, 2024 at 20:35 #2534
Hassan
MemberLets take an example,
constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;Now converting MyRecord to slv is quite simple. We just need to be sure that we do it the same way everywhere or better write a function. If the value of field length changes, there is no problem here:
slv := field1 & field2 & field3;Now converting from slv to MyRecord is not straightforward since it needs many lines of code.
— Function to convert std_logic_vector to MyRecord
function to_MyRecord(slv : std_logic_vector(11 downto 0)) return MyRecord is
variable rec : MyRecord;
begin
rec.field1 := slv(field3_len+field2_len);
rec.field2 := slv(field3_len+field2_len-1 downto field3_len);
rec.field3 := slv(field3_len-1 downto 0);
return rec;
end function;Now writing these functions takes time and is tedious. If the record changes we need to update all the functions. The biggest problem is that if we have records with a large number of fields and a new field is added in the middle (just we need to do that sometimes for reasons outside of control), then it is quite easy to make mistake in the modifying of slv to record function.
SystemVerilog does not need this type of conversion. My question is, why doesn’t VHDL provide a built in method to convert from slv to record?
July 20, 2024 at 00:59 #2536Jim Lewis
MemberHi Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/
VHDL in particular is a volunteer driven standard. Hence, it is important that you do participate.
Best Regards,
JimJuly 24, 2024 at 13:30 #2537Hassan
MemberOne more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than half of it.
Anyway, I shall keep https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/ in mind.
July 29, 2024 at 19:44 #2548Jim Lewis
MemberYes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.
Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.
July 30, 2024 at 12:52 #2549Hassan
MemberI am just wondering how come the big names like Siemes, Mentor Graphics e.t.c don’t fund this group. Also, the government does not seem to show any keen interest to fund this. The evolution of technology requires tools to be in place. If the industry giants don’t come together to make it happen, who else is going to make it happen?
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