The #if in VHDL

[Hassan]

I worked at an organization that designed very large digital designs, so large that no FPGA can fit them, millions and millions of gates. These designs had a lot of features that could be enabled or disabled using something they called configurations. A configuration would add or remove or change ports of interfaces. These would also affect other parts of RTL code.

All the configuration work relied on use of #if. In SystemVerilog, this worked the same way as C++. If the condition in #if is not true, the enclosed code of that #if block is not considered by the synthesis and simulation tools and basically just ignored as if it does not exist. In VHDL we do not have this feature.

Although VHDL has “generate” blocks, it is not the same as the #if. The company used dozens of #if anyway in RTL files that would often be thousands of lines. They did this in VHDL files and named those files .vhdm. Then another tool would process these files and strip out parts that are to be excluded based on the #if and configuration of the design that has been chosen to be simulated or synthesized. Then a normal .vhd file would be created after this code stripping and this normal .vhd would be used for synthesis and simulation.

My question is, why does VHDL not have this #if capability? It is something quite powerful and must have been adopted from the software programming language domain more than 30 years ago when VHDL was being created.

[Jim Lewis]

Hi Hassan,
It is part of VHDL-2019. It is called Conditional Analysis. I have heard that vendors support it in older revisions. Even vendors who make no claims about supporting VHDL-2019.

For details, see my presentation, VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and Environment. I did this through Aldec as one of their events. You should be able to register with them and watch it.

For the example from the presentation, see: https://gitlab.com/synthworks/VHDL_2019 then ConditionalAnalysis

Best Regards,
Jim

[Hassan]

Doesn’t that feature only work with these things:

`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;

How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.

I mean using #if we can add ports, strip ports, include or exclude things as basic as a + or – sign or semicolon. Without #if, it would be impossible to generate all the different versions of design from that same source code. It is truly mind blowing what this feature can actually make possible.

[Hassan]

If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:

#if FEATURE1

#endif

#if FEATURE2

#if FEATURE3VER > 2

#else

#endif

#endif

How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be defined, as constants?

The ability to add or remove ports using #if in SystemVerilog is rather interesting. I believe that it does not exist in VHDL so far, maybe something like it now exists in VHDL-2019 Conditional Analysis.

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