VHDL Assert that prints the entity instance name and path

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  • #2497
    Hassan
    Member

    This question is specifically about Assert used to validate the generics of VHDL entity. It is clear that one can use Assert statement to check the value of generic and if the assert fails, the synthesis will stop with error.

    There are two basic questions about this:

    1. Should such an Assert statement be inside or outside process? Different Synthesis and Simulation tools have some sort of order of precedance in which things are evaluated so this question arises.

    2. Is it possible to print the instance name of the entity where the assertion fails, into the error message, along with the entire hierarchy of the design upto this instance?

    I believe that some VHDL attribute exists for this but I am not sure of its correct usage and also whether it is a VHDL-2008 thing or also supported in earlier versions of the language. I am also not sure if this attribute is supported only by simulation ools or also synthesis tools and how many of them do not support it.

    #2498
    Hassan
    Member

    I have used these 3 attributes (simple_name, instance_name, path_name) in a process but it seems that Quartus synthesis does not support any of them at all. It just gives error “predefined attribute … is not supported”

    p_assert_generics: process
    begin

    report p_assert_generics’simple_name severity warning;
    report p_assert_generics’instance_name severity warning;
    report p_assert_generics’path_name severity warning;

    assert MAX_VALUE < 16
    report “MAX_VALUE is outside range”
    severity failure;
    wait;
    end process;

    From what I know, when we run synthesis, all processes in a design will run once.

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