How to improve VHDL

Why OSVVM™? Forums VHDL How to improve VHDL

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    Ian Gibbins

    Don’t like something in VHDL? Have new feature that you think should be added to VHDL?
    Let us know: just reply to this post below or create new topic…


    *Many people have been using for years the following three 

    Packages in almost any code they write:


    — classic package of Synopsys in old VHDL

    library ieee ;

    use ieee.std_logic_1164.all ;

    use ieee.std_logic_unsigned.all ;

    They make it possible to execute unsigned math operations on vectors

    in a convenient way with out all the clumsy casting operations

    or conversions needed when you use other vector-math packages.

    In VHDL-200 finally the previous 3 packages have been replaced with 

    the new standard packages, and the last package is more powerful 

    (for example enable division operations and more…).

    — same trio declarations with new package of IEEE in VHDL-2008

    library ieee ;

    use ieee.std_logic_1164.all ;

    use ieee.numeric_std_unsigned.all ; — a new package !

    This is very nice, but I can not find a replacement for the 

    Following useful trio: 

    — the signed trio

    library ieee ;

    use ieee.std_logic_1164.all ;

    use ieee.std_logic_signed.all ;

    Which enable signed math (for example when you want to

    make a compare operation and may other applications).


    Another request or wish would be to make this coding possible

    y <= a or b and c ; 

    — with the and operation done preceding the or operation and with no need for the flowing clumsy style y <= a or (b and c) ;

    This is actually the case when you write math operations

    m <= p + q * r ;

    Andy Jones


    1st issue: I have seen very few designs that use a signed numeric interpretation of every std_logic_vector in the design. Most designs that use signed interpretation also use unsigned interpretations, which would not be possible if such a package were used. If you need signed interpretations, it is best to use either integer subtypes or explicit signed data types to clearly define where signed interpretations and arithmetic are desired.

    2nd issue: Unlike the mathematical operators that have a widely accepted operator precedence, boolean operators do not. Therefore explicitly defining the desired precedence of boolean operators using parentheses provides an unambiguous description of the desired result. When you wrote “a or b and c” I had no idea whether you meant “(a or b) and c” or “a or (b and c)”. 

    Think less about how little you can type, and more about how clearly you can express the desired behavior. Those who will have to review, reuse or maintain your design will thank you for it.



    I still do not like the ambigious way, vectors are treated agains signals, and that there is conversion required in between a(0 downto 0) = “1” instead of using “a(0) = ‘1’). See the bram addressing regarding their write enable. This is one signal only, however one uses 0…0 instead of a signal. So VHDL could be made more tolerant for that.

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