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Tagged: external names
This topic has 3 voices, contains 3 replies, and was last updated by Fernando Domínguez 42 days ago.
Is it possible to use an external name in my testbench for a signal inside a record type signal?
This is my case:
My UUT has a signal like this:
type regs_type is record
— state machine
– other signals
regs : regs_type;
And I would like to access the state signal inside the record like this in the testbench:
alias fsm_state is <<signal .test.uut.regs.state : state_type >>;
I get the following error from Active-HDL:
# ELAB2: Fatal Error: ELAB2_0124 TC1SPW.vhd (224): Unresolved external name:
If I make a copy of the state signal in the UUT, it works fine. Is it a VHDL 2008 restriction or a limitation of the tool?
I would try making the external name reference the entire record. Then with a separate alias reference the state..
Thanks for the advice. It worked well. I just needed to move my record definition to a package that is visible from the UUT and my testbench.
I follow the 2-process method from Gaisler and I had the same error with Modelsim. The report message was:
“Illegal external name. ‘uut.r.state_top’ denotes an element of an array or record.”
I took your advice in mind, I moved my record definition to a package and then I added this code to testbench:
alias uut_r_register is << signal uut.r : fsm_wg_control_regs_t >>;
alias uut_state_top is uut_r_register.state_top;
It works well!
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