Is it possible to use an external name in my testbench for a signal inside a record type signal?
This is my case:
My UUT has a signal like this:
type regs_type is record
— state machine
— other signals
regs : regs_type;
And I would like to access the state signal inside the record like this in the testbench:
alias fsm_state is <<signal .test.uut.regs.state : state_type >>;
I get the following error from Active-HDL:
# ELAB2: Fatal Error: ELAB2_0124 TC1SPW.vhd (224): Unresolved external name:
If I make a copy of the state signal in the UUT, it works fine. Is it a VHDL 2008 restriction or a limitation of the tool?