The 2024.05 release adds: Report Updates SPI VC Additions Minor Updates Late Updates – after 2024.05 Report Updates OSVVM automatically generates HTML-based test suite reports, test case reports, and logs that facilitate debugging and provide detailed test artifact collection. OSVVM’s functional coverage reports rival those produced by SystemVerilog vendor tools. OSVVM’s R... »
We have a number of OSVVM class sessions coming up, including in person opportunities in Freiburg, Germany and Bracknell, UK – both of which I am teaching. In addition, we have numerous on-line, instructor led classes. These classes accelerate your learning pace of OSVVM. June 3 to 14 Online Class: 2 weeks, 10 class sessionsInstructor-led, live (interactive) session. Enroll with Sy... »
OSVVM 2024.03 updates can be summarized as: Settings/Configuration Updates Xilinx Update OSVVM Issues Resolved Added Verification Components Minor Updates OSVVM 2024.03a addresses an issue introduced in 2024.03 which calls EndSimulation when a simulation finishes with a TCL error code. This allows VHDL files to be closed that were not properly closed when the simulator exited. Unfortunately... »
Quite some time ago I tried out AMD/Xilinx XSIM in OSVVM. Unfortunately at the time, it was like the Talking Heads song – “We’re on a road to no where” Things have changed. We have heard good things about Vivado Synthesis starting to support VHDL-2019 features – like interfaces. Hear that Siemen’s? Are you going to let AMD Vivado pass you as well as Aldec? So my... »
2023 brought lots of changes. I started traveling again (a little bit). This was my first travels since the start of COVID. I presented papers on OSVVM at SEFUW (ESA’s Space FPGA Users Workshop), MAPLD (NASA’s Military and Aerospace Programmable Logic Devices), FPGA Conference Europe (in Munich), and at Verification Futures (both in Reading UK and Austin TX). OSVVM had 5 updates during... »
The 2023.09a release adds: Scripts: build/include now support Early detection of file or path not found and better error messages. $::ARGV (a TCL array) and $::ARGC $::argv (a TCL list), $::argc and $::argv0 OsvvmSettingsPkg: Package with deferred constants to configure OSVVM settings. RandomPkg – Provides the default value for InitSeed UseNewSeedMethods. AlertLogPkg – Provides the def... »
Summary of 2023.01 Changes Co-simulation environment that supports running software (C++) in a hardware simulation environment. Added OsvvmScriptSettings.vhd to the OSVVM utility library. Autogenerated when the OSVVM library is analyzed. Script settings with the OSVVM library Added Interrupt generator and updated interrupt handling. Added PassThru VC for Axi4, Axi4Lite, and AxiStream to act... »
Summary of 2022.12 Changes Updated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found Updated scripts for Synopsys VCS and Cadence Xcelium Updated log file creation to first use OsvvmBuild.log and then it is copied to “LogFileDirectory”/”BuildName”.log. Updated Generic Handling Both Simulate and RunTest support callin... »
As I was writing the blog about the 2022.10 Multiple Verification Component example, my focus was drawn to the issue, “How do I call transactions that iterate across an array of verification components?” Solving this issue became the main goal of the 2022.11 release. The 2022.11 release includes: Updated Multiple Verification Component Test Example Created AddressBus and Stream transac... »
Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas. For the 2022.10 release, I prepared a basic example that instances 16 UartTx and UartRx components. The good thing about writing test cases like this is that it reveals further opportunities for improvements. As I wrote this a... »