It seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three weeks now. A big part of that is because as soon as I got back, I have been focused on the OSVVM 2024.07 release – and I tend to get tunnel vision. Verification Futures Conference – June 18 On June 18th I presented Essential ... »
OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This capability is important when the verification component is embedded in the design – such as an embedded processor like ZYNQ. In this situation, we want to avoid adding “testben... »
2020 was quite a year. While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) went into enhancing OSVVM. OSVVM had 6 updates in 2020. This includes the 2020.12 revision which was released late on December 31. More on 2020.12 in a future post. Here are some milestones t... »
It has been a busy summer for OSVVM. With the world working out of home offices, all of our training has shifted to on-line – which fortunately we started doing 7+ years ago. Not having to travel has freed up additional time that I have devoted to OSVVM development. Updates started with adding PASSED counts to the AlertLog data structure in 2020.05. AXI Full verification components (ma... »
Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, AxiStream, and UART models were updated to use the new OSVVM Model Independent Transactions. AXI4 (and Axi4Lite) verification components are the most challenging and most interesting I have worked on. O... »
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record? In this article we will explore how to do this with either VHDL-2019 interfaces or OSVVM interfaces. VHDL-2019 Interfaces Step 1: A Record is the foundation VHDL-2019 interfaces start with a recor... »
Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. This webinar is a guided walk-through of the OSVVM verification framework and transac... »