Abstract Some methodologies (or frameworks) are so complex that you need a script to create initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their “Lite” or “Easy” approach. Creating a verification component (VC) using OS... »
Ready to go the next step with OSVVM? OSVVM training is available on-line. Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL training for 20+ years and on-line training for 7+ years. So don’t worry, we go this. Your on-line class session will be great. Our on-line class sessions are offered in a relaxing “hal... »
Coming to DAC? I will be hosting an OSVVM birds of feather (BOF) / community meeting. The meeting is intended to provide the opportunity to learn more and discus future directions of OSVVM. It is on Tuesday evening June 9 from 7 pm to 8:30 pm in Room 300 »
Release 2014.07 has been posted on the downloads pages. Its main target is interfacing with requirements tools. Added names to bins (via AddBins and AddCross). It is intended that the name match a requirement name. When using WriteBin or WriteCovHoles, if a bin name is set, it will print. For details, see Setting Bin Names in the Reporting Coverage section of the CoveragePkg Users Guide. Enhanced ... »
Recently Matthias Alles of Creonic shared his OSVVM usage story. I would like to invite you to share how you are using OSVVM. Send a copy of your proposed article to myself (jim at SynthWorks) or Jerry (Jerry at Aldec). From there we can get you setup to post it to the blog. »
OSVVM release 2013.04 is now available at OSVVM Downloads. »