The 2025.06 release adds: Build Directories Tcl procedure CreateTestCaseCommonPkg Tcl procedure RunAllTests Questa – new vs. old script flows Clock edge specification for WaitForClock, WaitForTransaction, … Most VC Test Cases updated Build Directories All build output is now collected into a build directory. The default name for is DirName_ScriptName. Set the name with BuildName... »
The 2024 Wilson Verification survey shows that OSVVM is being used by 35% of all FPGA designers world-wide, which makes OSVVM VHDL’s #1 Verification Methodology. Year after year we have made steady gains on UVM (SystemVerilog) in FPGA Verification. In Europe for FPGA, the 2022 survey showed that OSVVM is used more than UVM (38% to 20%). Here are a few reasons why you should be using O... »
I am often asked does OSVVM work in XSIM? With the upcoming OSVVM 2025.02 release – YES!!! As I was wrapping up on OSVVM 2025.02 release, inspired by another instance of this question, I decided to take a look at XSIM 2024.2. »
Recorded Webinars. Why Should Our Team be Using VHDL + OSVVM for Verification? Recording of the session Using OSVVM’s AXI4 Verification Components Part 1 – Creating the AXI4 Testbench (Test Harness) Recording of the session Using OSVVM’s AXI4 Verification Components Part 2 – Writing Tests and Configuring the AXI4 VCs Recording of the session Upcoming OSVVM class sessions.... »
It seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three weeks now. A big part of that is because as soon as I got back, I have been focused on the OSVVM 2024.07 release – and I tend to get tunnel vision. Verification Futures Conference – June 18 On June 18th I presented Essential ... »
The 2024.05 release adds: Report Updates SPI VC Additions Minor Updates Late Updates – after 2024.05 Report Updates OSVVM automatically generates HTML-based test suite reports, test case reports, and logs that facilitate debugging and provide detailed test artifact collection. OSVVM’s functional coverage reports rival those produced by SystemVerilog vendor tools. OSVVM’s R... »
Ready to go the next step with OSVVM? OSVVM training is available on-line and on-site. Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL training for 25+ years and on-line training for 10+ years. So don’t worry, we got this. Your on-line class session will be great. Our on-line class sessions are offered in a relax... »
OSVVM 2024.03 updates can be summarized as: Settings/Configuration Updates Xilinx Update OSVVM Issues Resolved Added Verification Components Minor Updates OSVVM 2024.03a addresses an issue introduced in 2024.03 which calls EndSimulation when a simulation finishes with a TCL error code. This allows VHDL files to be closed that were not properly closed when the simulator exited. Unfortunately... »
Quite some time ago I tried out AMD/Xilinx XSIM in OSVVM. Unfortunately at the time, it was like the Talking Heads song – “We’re on a road to no where” Things have changed. We have heard good things about Vivado Synthesis starting to support VHDL-2019 features – like interfaces. Hear that Siemen’s? Are you going to let AMD Vivado pass you as well as Aldec? So my... »
2023 brought lots of changes. I started traveling again (a little bit). This was my first travels since the start of COVID. I presented papers on OSVVM at SEFUW (ESA’s Space FPGA Users Workshop), MAPLD (NASA’s Military and Aerospace Programmable Logic Devices), FPGA Conference Europe (in Munich), and at Verification Futures (both in Reading UK and Austin TX). OSVVM had 5 updates during... »